1. 04 Mar, 2008 8 commits
  2. 03 Mar, 2008 6 commits
  3. 02 Mar, 2008 23 commits
  4. 27 Feb, 2008 3 commits
    • Kumar Gala's avatar
      85xx: Don't icbi when unlocking the cache · 2b22fa4b
      Kumar Gala authored
      
      
      There is no reason to icbi when invalidating the temporary stack in
      the d-cache.  Its impossible on e500 to have the i-cache contain
      any addresses in the temp stack and it can be problematic in generating
      transactions on the bus to non-valid addresses.
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      2b22fa4b
    • Andy Fleming's avatar
      Fix source for ECM error IVPR · 534ea6b6
      Andy Fleming authored
      
      
      The source vector for the ECM was being set to 2,
      but that's what the source vector for DDR was being
      set to.  Change it to 1.
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      534ea6b6
    • Andy Fleming's avatar
      Invalidate INIT_RAM TLB mappings · 21fae8b2
      Andy Fleming authored
      Commit 0db37dc2
      
      ...  (and some others) changed the INIT_RAM TLB
      mappings to be unguarded.  This collided with an existing "bug"
      where the mappings for the INIT_RAM were being kept around.
      This meant that speculative loads to those addresses were
      succeeding in the TLB, and going out to the bus, where they
      were causing an exception (there's nothing at that address). The
      Flash code was coincidentally causing such a speculative load.
      Rather than go back to mapping the INIT RAM as guarded, we fix
      it so that the entries for the INIT_RAM are invalidated.  Thus
      the speculative loads will fail in the TLB, and have no effect.
      Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
      21fae8b2