rockchip: rk3188: Add core support

Add the core architecture code for the rk3188.
It doesn't support the SPL yet, as because of some
unknown error it doesn't start yet.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Drop these defines from rk3188_common.h
   CONFIG_GENERIC_MMC, CONFIG_BOUNCE_BUFFER, CONFIG_DOS_PARTITION
   CONFIG_PARTITION_UUIDS, CONFIG_CMD_PART:
Signed-off-by: Simon Glass <sjg@chromium.org>

arch/arm/mach-rockchip/Kconfig

@@ -11,6 +11,21 @@ config ROCKCHIP_RK3036
 	  and video codec support. Peripherals include Gigabit Ethernet,
 	  USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
 
+config ROCKCHIP_RK3188
+	bool "Support Rockchip RK3188"
+	select CPU_V7
+	select SUPPORT_SPL
+	select SUPPORT_TPL
+	select SPL
+	select TPL
+	select ROCKCHIP_BROM_HELPER
+	help
+	  The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
+	  including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
+	  video interfaces, several memory options and video codec support.
+	  Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
+	  UART, SPI, I2C and PWMs.
+
 config ROCKCHIP_RK3288
 	bool "Support Rockchip RK3288"
 	select CPU_V7
@@ -50,6 +65,7 @@ config SPL_MMC_SUPPORT
 	default y if !ROCKCHIP_SPL_BACK_TO_BROM
 
 source "arch/arm/mach-rockchip/rk3036/Kconfig"
+source "arch/arm/mach-rockchip/rk3188/Kconfig"
 source "arch/arm/mach-rockchip/rk3288/Kconfig"
 source "arch/arm/mach-rockchip/rk3399/Kconfig"
 endif

arch/arm/mach-rockchip/Makefile

@@ -16,5 +16,10 @@ ifndef CONFIG_ARM64
 obj-y += rk_timer.o
 endif
 obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
+
+ifndef CONFIG_TPL_BUILD
+obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/
+endif
+
 obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
 obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/

arch/arm/mach-rockchip/rk3188/Kconfig

+if ROCKCHIP_RK3188
+
+config SYS_SOC
+	default "rockchip"
+
+config SYS_MALLOC_F_LEN
+	default 0x0800
+
+config SPL_LIBCOMMON_SUPPORT
+	default y
+
+config SPL_LIBGENERIC_SUPPORT
+	default y
+
+config SPL_SERIAL_SUPPORT
+	default y
+
+config TPL_LIBCOMMON_SUPPORT
+	default y
+
+config TPL_SERIAL_SUPPORT
+	default y
+
+endif

arch/arm/mach-rockchip/rk3188/Makefile

+#
+# Copyright (c) 2015 Google, Inc
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+ifndef CONFIG_TPL_BUILD
+obj-y += clk_rk3188.o
+obj-y += syscon_rk3188.o
+endif

arch/arm/mach-rockchip/rk3188/clk_rk3188.c

+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3188.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+	return uclass_get_device_by_driver(UCLASS_CLK,
+			DM_GET_DRIVER(rockchip_rk3188_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+	struct rk3188_clk_priv *priv;
+	struct udevice *dev;
+	int ret;
+
+	ret = rockchip_get_clk(&dev);
+	if (ret)
+		return ERR_PTR(ret);
+
+	priv = dev_get_priv(dev);
+
+	return priv->cru;
+}

arch/arm/mach-rockchip/rk3188/syscon_rk3188.c

+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+
+static const struct udevice_id rk3188_syscon_ids[] = {
+	{ .compatible = "rockchip,rk3188-noc", .data = ROCKCHIP_SYSCON_NOC },
+	{ .compatible = "rockchip,rk3188-grf", .data = ROCKCHIP_SYSCON_GRF },
+	{ .compatible = "rockchip,rk3188-pmu", .data = ROCKCHIP_SYSCON_PMU },
+	{ }
+};
+
+U_BOOT_DRIVER(syscon_rk3188) = {
+	.name = "rk3188_syscon",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3188_syscon_ids,
+};
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+static int rk3188_syscon_bind_of_platdata(struct udevice *dev)
+{
+	dev->driver_data = dev->driver->of_match->data;
+	debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(rockchip_rk3188_noc) = {
+	.name = "rockchip_rk3188_noc",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3188_syscon_ids,
+	.bind = rk3188_syscon_bind_of_platdata,
+};
+
+U_BOOT_DRIVER(rockchip_rk3188_grf) = {
+	.name = "rockchip_rk3188_grf",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3188_syscon_ids + 1,
+	.bind = rk3188_syscon_bind_of_platdata,
+};
+
+U_BOOT_DRIVER(rockchip_rk3188_pmu) = {
+	.name = "rockchip_rk3188_pmu",
+	.id = UCLASS_SYSCON,
+	.of_match = rk3188_syscon_ids + 2,
+	.bind = rk3188_syscon_bind_of_platdata,
+};
+#endif

include/configs/rk3188_common.h

+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#ifndef __CONFIG_RK3188_COMMON_H
+#define __CONFIG_RK3188_COMMON_H
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+#include <asm/arch/hardware.h>
+#include "rockchip-common.h"
+
+#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_MALLOC_LEN		(32 << 20)
+#define CONFIG_SYS_CBSIZE		1024
+#define CONFIG_SYS_THUMB_BUILD
+
+#define CONFIG_SYS_TIMER_RATE		(24 * 1000 * 1000)
+#define CONFIG_SYS_TIMER_BASE		0x2000e000 /* TIMER3 */
+#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMER_BASE + 8)
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SPL_BOARD_INIT
+
+#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM
+/* Bootrom will load u-boot binary to 0x60000000 once return from SPL */
+#define CONFIG_SYS_TEXT_BASE		0x60000000
+#else
+#define CONFIG_SYS_TEXT_BASE		0x60100000
+#endif
+#define CONFIG_SYS_INIT_SP_ADDR		0x60100000
+#define CONFIG_SYS_LOAD_ADDR		0x60800800
+
+#define CONFIG_ROCKCHIP_MAX_INIT_SIZE	(0x8000 - 0x800)
+#define CONFIG_ROCKCHIP_CHIP_TAG	"RK31"
+
+#ifdef CONFIG_TPL_BUILD
+#define CONFIG_SPL_TEXT_BASE		0x10080804
+/* tpl size 1kb - 4byte RK31 header */
+#define CONFIG_SPL_MAX_SIZE		(0x400 - 0x4)
+#elif defined(CONFIG_SPL_BUILD)
+/* spl size 32kb sram - 2kb bootrom - 1kb spl */
+#define CONFIG_SPL_MAX_SIZE		(0x8000 - 0xC00)
+#define CONFIG_SPL_TEXT_BASE		0x10080C00
+#define CONFIG_SPL_FRAMEWORK		1
+#define CONFIG_SPL_CLK			1
+#define CONFIG_SPL_PINCTRL		1
+#define CONFIG_SPL_REGMAP		1
+#define CONFIG_SPL_SYSCON		1
+#define CONFIG_SPL_RAM			1
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT	1
+#define CONFIG_ROCKCHIP_SERIAL		1
+#endif
+
+#define CONFIG_SPL_STACK		0x10087fff
+
+/* MMC/SD IP block */
+#define CONFIG_BOUNCE_BUFFER
+
+#define CONFIG_FAT_WRITE
+
+#define CONFIG_SYS_SDRAM_BASE		0x60000000
+#define CONFIG_NR_DRAM_BANKS		1
+#define SDRAM_BANK_SIZE			(2UL << 30)
+
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI
+#define CONFIG_SF_DEFAULT_SPEED 20000000
+
+#ifndef CONFIG_SPL_BUILD
+/* usb otg */
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_DWC2_OTG
+#define CONFIG_ROCKCHIP_USB2_PHY
+#define CONFIG_USB_GADGET_VBUS_DRAW	0
+
+#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_G_DNL_MANUFACTURER	"Rockchip"
+#define CONFIG_G_DNL_VENDOR_NUM		0x2207
+#define CONFIG_G_DNL_PRODUCT_NUM	0x310a
+
+/* usb host support */
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_DWC2
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_ETHER_ASIX
+#endif
+#define ENV_MEM_LAYOUT_SETTINGS \
+	"scriptaddr=0x60000000\0" \
+	"pxefile_addr_r=0x60100000\0" \
+	"fdt_addr_r=0x61f00000\0" \
+	"kernel_addr_r=0x62000000\0" \
+	"ramdisk_addr_r=0x64000000\0"
+
+#include <config_distro_bootcmd.h>
+
+/* Linux fails to load the fdt if it's loaded above 256M on a Rock board,
+ * so limit the fdt reallocation to that */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdt_high=0x6fffffff\0" \
+	"initrd_high=0x6fffffff\0" \
+	"partitions=" PARTS_DEFAULT \
+	ENV_MEM_LAYOUT_SETTINGS \
+	ROCKCHIP_DEVICE_SETTINGS \
+	BOOTENV
+
+#endif /* CONFIG_SPL_BUILD */
+
+#define CONFIG_PREBOOT
+
+#endif