Commit c36643ff authored by Hou Zhiqiang's avatar Hou Zhiqiang Committed by Prabhakar Kushwaha
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powerpc: Enable device tree support for P2041RDB



Add device tree for P1041RDB board and enable CONFIG_OF_CONTROL
so that device tree can be compiled.
Update board README for device tree usage.
Signed-off-by: default avatarHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: default avatarPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
parent caa75697
......@@ -3,6 +3,7 @@
dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb
dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb
dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb
dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
......
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* e500mc Power ISA Device Tree Source (include)
*
* Copyright 2012 Freescale Semiconductor Inc.
* Copyright 2019 NXP
*/
/ {
cpus {
power-isa-version = "2.06";
power-isa-b; // Base
power-isa-e; // Embedded
power-isa-atb; // Alternate Time Base
power-isa-cs; // Cache Specification
power-isa-ds; // Decorated Storage
power-isa-e.ed; // Embedded.Enhanced Debug
power-isa-e.pd; // Embedded.External PID
power-isa-e.hv; // Embedded.Hypervisor
power-isa-e.le; // Embedded.Little-Endian
power-isa-e.pm; // Embedded.Performance Monitor
power-isa-e.pc; // Embedded.Processor Control
power-isa-ecl; // Embedded Cache Locking
power-isa-exp; // External Proxy
power-isa-fp; // Floating Point
power-isa-fp.r; // Floating Point.Record
power-isa-mmc; // Memory Coherence
power-isa-scpm; // Store Conditional Page Mobility
power-isa-wt; // Wait
fsl,eref-deo; // Data Cache Extended Operations
mmu-type = "power-embedded";
};
};
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P2041 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
*/
/dts-v1/;
/include/ "e500mc_power_isa.dtsi"
/ {
compatible = "fsl,P2041";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: PowerPC,e500mc@0 {
device_type = "cpu";
reg = <0>;
fsl,portid-mapping = <0x80000000>;
};
cpu1: PowerPC,e500mc@1 {
device_type = "cpu";
reg = <1>;
fsl,portid-mapping = <0x40000000>;
};
cpu2: PowerPC,e500mc@2 {
device_type = "cpu";
reg = <2>;
fsl,portid-mapping = <0x20000000>;
};
cpu3: PowerPC,e500mc@3 {
device_type = "cpu";
reg = <3>;
fsl,portid-mapping = <0x10000000>;
};
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <4>;
reg = <0x40000 0x40000>;
compatible = "fsl,mpic", "chrp,open-pic";
device_type = "open-pic";
clock-frequency = <0x0>;
};
};
};
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P2041RDB Device Tree Source
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
*/
/include/ "p2041.dtsi"
/ {
model = "fsl,P2041RDB";
compatible = "fsl,P2041RDB";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
};
......@@ -85,6 +85,24 @@ Boot from SPI flash
SW1[1-5] = 10100
Note: 1 stands for 'on', 0 stands for 'off'
Device tree support and how to enable it for different configs
--------------------------------------------------------------
Device tree support is available for p2041rdb for below mentioned boot,
1. NOR Boot
2. NAND Boot
3. SD Boot
4. SPIFLASH Boot
To enable device tree support for other boot, below configs need to be
enabled in relative defconfig file,
1. CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" (Change default device tree name if required)
2. CONFIG_OF_CONTROL
3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
CONFIG_RESET_VECTOR_ADDRESS - 0xffc
If device tree support is enabled in defconfig, use 'u-boot-with-dtb.bin'
instead of u-boot.bin for all boot.
CPLD command
============
The CPLD is used to control the power sequence and some serdes lane
......
......@@ -2,6 +2,7 @@ CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
......@@ -23,6 +24,8 @@ CONFIG_CMD_PING=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
......@@ -46,4 +49,3 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
......@@ -2,6 +2,7 @@ CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
......@@ -23,6 +24,8 @@ CONFIG_CMD_PING=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
......@@ -45,4 +48,3 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
......@@ -2,6 +2,7 @@ CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
......@@ -23,6 +24,8 @@ CONFIG_CMD_PING=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
......@@ -45,4 +48,3 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
......@@ -2,6 +2,7 @@ CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
......@@ -22,6 +23,8 @@ CONFIG_CMD_PING=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
......@@ -44,4 +47,3 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y
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