Commit c3c0331d authored by Kever Yang's avatar Kever Yang Committed by Philipp Tomsich
Browse files

rockchip: enable SYS_NS16550 for all SoCs by default



All rockchip SoCs can use ns16550 driver, enable it for all
and set SYS_NS16550_MEM32 for all SoCs.

Version-changes: 2
- use imply instead of select
Signed-off-by: Kever Yang's avatarKever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich's avatarPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich's avatarPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>
parent 932b2c98
......@@ -1185,6 +1185,7 @@ config ARCH_ROCKCHIP
imply TPL_SYSRESET
imply ADC
imply SARADC_ROCKCHIP
imply SYS_NS16550
config TARGET_THUNDERX_88XX
bool "Support ThunderX 88xx"
......
......@@ -103,7 +103,6 @@ config ROCKCHIP_RK3368
imply SPL_SERIAL_SUPPORT
imply TPL_SERIAL_SUPPORT
select DEBUG_UART_BOARD_INIT
select SYS_NS16550
help
The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
into a big and little cluster with 4 cores each) Cortex-A53 including
......
......@@ -18,9 +18,6 @@
#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
#define CONFIG_SYS_LOAD_ADDR 0x60800800
#define CONFIG_SPL_STACK 0x10081fff
......
......@@ -19,8 +19,6 @@
#define CONFIG_SYS_TIMER_BASE 0x200440a0 /* TIMER5 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
#define CONFIG_SYS_LOAD_ADDR 0x60800800
......
......@@ -18,7 +18,6 @@
#define CONFIG_SYS_TIMER_BASE 0x110c00a0 /* TIMER5 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_INIT_SP_ADDR 0x60100000
#define CONFIG_SYS_LOAD_ADDR 0x60800800
#define CONFIG_SPL_STACK 0x10088000
......
......@@ -19,8 +19,6 @@
#define CONFIG_SYS_TIMER_BASE 0xff810020 /* TIMER7 */
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SYS_NS16550_MEM32
#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM
/* Bootrom will load u-boot binary to 0x0 once return from SPL */
#endif
......
......@@ -18,9 +18,6 @@
#define CONFIG_SYS_TIMER_BASE 0x10350020
#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_SDRAM_BASE 0x60000000
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000)
......
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