Commit d877f8fd authored by Marek Szyprowski's avatar Marek Szyprowski Committed by Tom Rini
Browse files

arm: provide a function for boards init code to modify MMU virtual-physical map



Provide function for setting arbitrary virtual-physical MMU mapping
and cache settings for the given region.
Signed-off-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Tom Rini's avatarTom Rini <trini@konsulko.com>
parent f5a9fcc6
/* SPDX-License-Identifier: GPL-2.0+ */
#ifndef __ASM_ARM_MMU_H
#define __ASM_ARM_MMU_H
void init_addr_map(void);
#endif
......@@ -587,6 +587,19 @@ s32 psci_features(u32 function_id, u32 psci_fid);
*/
void save_boot_params_ret(void);
/**
* mmu_set_region_dcache_behaviour_phys() - set virt/phys mapping
*
* Change the virt/phys mapping and cache settings for a region.
*
* @virt: virtual start address of memory region to change
* @phys: physical address for the memory region to set
* @size: size of memory region to change
* @option: dcache option to select
*/
void mmu_set_region_dcache_behaviour_phys(phys_addr_t virt, phys_addr_t phys,
size_t size, enum dcache_option option);
/**
* mmu_set_region_dcache_behaviour() - set cache settings
*
......
......@@ -25,7 +25,8 @@ __weak void arm_init_domains(void)
{
}
void set_section_dcache(int section, enum dcache_option option)
static void set_section_phys(int section, phys_addr_t phys,
enum dcache_option option)
{
#ifdef CONFIG_ARMV7_LPAE
u64 *page_table = (u64 *)gd->arch.tlb_addr;
......@@ -37,7 +38,7 @@ void set_section_dcache(int section, enum dcache_option option)
#endif
/* Add the page offset */
value |= ((u32)section << MMU_SECTION_SHIFT);
value |= phys;
/* Add caching bits */
value |= option;
......@@ -46,13 +47,18 @@ void set_section_dcache(int section, enum dcache_option option)
page_table[section] = value;
}
void set_section_dcache(int section, enum dcache_option option)
{
set_section_phys(section, (u32)section << MMU_SECTION_SHIFT, option);
}
__weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
{
debug("%s: Warning: not implemented\n", __func__);
}
void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
enum dcache_option option)
void mmu_set_region_dcache_behaviour_phys(phys_addr_t start, phys_addr_t phys,
size_t size, enum dcache_option option)
{
#ifdef CONFIG_ARMV7_LPAE
u64 *page_table = (u64 *)gd->arch.tlb_addr;
......@@ -74,8 +80,8 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
option);
#endif
for (upto = start; upto < end; upto++)
set_section_dcache(upto, option);
for (upto = start; upto < end; upto++, phys += MMU_SECTION_SIZE)
set_section_phys(upto, phys, option);
/*
* Make sure range is cache line aligned
......@@ -90,6 +96,12 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
mmu_page_table_flush(startpt, stoppt);
}
void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
enum dcache_option option)
{
mmu_set_region_dcache_behaviour_phys(start, start, size, option);
}
__weak void dram_bank_mmu_setup(int bank)
{
bd_t *bd = gd->bd;
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment