Commit e4b8dd9b authored by Tom Rini's avatar Tom Rini
Browse files

Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx

Support of device tree model for T2080RDB, T4240RDB, T1024RDB,
T1042D4RDB, P1020RDB, P2020RDB, P2041RDB, P3041DS, P4080DS, P5040DS and
MPC8548CDS. Also support of  i2c dm model.
parents e7ce2e04 f83c7788
......@@ -1256,10 +1256,16 @@ MKIMAGEFLAGS_u-boot-spl.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy)
UBOOT_BIN := u-boot-with-dtb.bin
else
UBOOT_BIN := u-boot.bin
endif
u-boot-dtb.img u-boot.img u-boot.kwb u-boot.pbl u-boot-ivt.img: \
$(if $(CONFIG_SPL_LOAD_FIT),u-boot-nodtb.bin \
$(if $(CONFIG_OF_SEPARATE)$(CONFIG_OF_EMBED)$(CONFIG_OF_HOSTFILE),dts/dt.dtb) \
,u-boot.bin) FORCE
,$(UBOOT_BIN)) FORCE
$(call if_changed,mkimage)
$(BOARD_SIZE_CHECK)
......
# SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PC) += p1020rdb-pc.dtb p1020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_P1020RDB_PD) += p1020rdb-pd.dtb
dtb-$(CONFIG_TARGET_P2020RDB) += p2020rdb-pc.dtb p2020rdb-pc_36b.dtb
dtb-$(CONFIG_TARGET_P2041RDB) += p2041rdb.dtb
dtb-$(CONFIG_TARGET_P3041DS) += p3041ds.dtb
dtb-$(CONFIG_TARGET_P4080DS) += p4080ds.dtb
dtb-$(CONFIG_TARGET_P5040DS) += p5040ds.dtb
dtb-$(CONFIG_TARGET_T1024RDB) += t1024rdb.dtb
dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb
dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
dtb-$(CONFIG_TARGET_T2080RDB) += t2080rdb.dtb
dtb-$(CONFIG_TARGET_T4240RDB) += t4240rdb.dtb
dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb
dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb
......
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* e500mc Power ISA Device Tree Source (include)
*
* Copyright 2012 Freescale Semiconductor Inc.
* Copyright 2019 NXP
*/
/ {
cpus {
power-isa-version = "2.06";
power-isa-b; // Base
power-isa-e; // Embedded
power-isa-atb; // Alternate Time Base
power-isa-cs; // Cache Specification
power-isa-ds; // Decorated Storage
power-isa-e.ed; // Embedded.Enhanced Debug
power-isa-e.pd; // Embedded.External PID
power-isa-e.hv; // Embedded.Hypervisor
power-isa-e.le; // Embedded.Little-Endian
power-isa-e.pm; // Embedded.Performance Monitor
power-isa-e.pc; // Embedded.Processor Control
power-isa-ecl; // Embedded Cache Locking
power-isa-exp; // External Proxy
power-isa-fp; // Floating Point
power-isa-fp.r; // Floating Point.Record
power-isa-mmc; // Memory Coherence
power-isa-scpm; // Store Conditional Page Mobility
power-isa-wt; // Wait
fsl,eref-deo; // Data Cache Extended Operations
mmu-type = "power-embedded";
};
};
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* e500v2 Power ISA Device Tree Source (include)
*
* Copyright 2012 Freescale Semiconductor Inc.
* Copyright 2019 NXP
*/
/ {
cpus {
power-isa-version = "2.03";
power-isa-b; // Base
power-isa-e; // Embedded
power-isa-atb; // Alternate Time Base
power-isa-cs; // Cache Specification
power-isa-e.le; // Embedded.Little-Endian
power-isa-e.pm; // Embedded.Performance Monitor
power-isa-ecl; // Embedded Cache Locking
power-isa-mmc; // Memory Coherence
power-isa-sp; // Signal Processing Engine
power-isa-sp.fd; // SPE.Embedded Float Scalar Double
power-isa-sp.fs; // SPE.Embedded Float Scalar Single
power-isa-sp.fv; // SPE.Embedded Float Vector
mmu-type = "power-embedded";
};
};
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* e5500 Power ISA Device Tree Source (include)
*
* Copyright 2012 Freescale Semiconductor Inc.
* Copyright 2019 NXP
*/
/ {
cpus {
power-isa-version = "2.06";
power-isa-b; // Base
power-isa-e; // Embedded
power-isa-atb; // Alternate Time Base
power-isa-cs; // Cache Specification
power-isa-ds; // Decorated Storage
power-isa-e.ed; // Embedded.Enhanced Debug
power-isa-e.pd; // Embedded.External PID
power-isa-e.hv; // Embedded.Hypervisor
power-isa-e.le; // Embedded.Little-Endian
power-isa-e.pm; // Embedded.Performance Monitor
power-isa-e.pc; // Embedded.Processor Control
power-isa-ecl; // Embedded Cache Locking
power-isa-exp; // External Proxy
power-isa-fp; // Floating Point
power-isa-fp.r; // Floating Point.Record
power-isa-mmc; // Memory Coherence
power-isa-scpm; // Store Conditional Page Mobility
power-isa-wt; // Wait
power-isa-64; // 64-bit
fsl,eref-deo; // Data Cache Extended Operations
mmu-type = "power-embedded";
};
};
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* MPC8548 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2012 Freescale Semiconductor Inc.
* Copyright 2019 NXP
*/
&soc {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,mpc8548-immr", "simple-bus";
bus-frequency = <0x0>;
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <4>;
reg = <0x40000 0x40000>;
compatible = "fsl,mpic";
device_type = "open-pic";
big-endian;
single-cpu-affinity;
last-interrupt-source = <255>;
};
};
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* MPC8548CDS Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2019 NXP
*/
/dts-v1/;
/include/ "e500v2_power_isa.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
PowerPC,8548@0 {
device_type = "cpu";
reg = <0>;
};
};
};
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* MPC8548CDS Device Tree Source
*
* Copyright 2006 - 2012 Freescale Semiconductor Inc.
* Copyright 2019 NXP
*/
/include/ "mpc8548.dtsi"
/ {
model = "fsl,MPC8548CDS";
compatible = "fsl,MPC8548CDS";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
soc: soc8548@e0000000 {
ranges = <0x0 0x0 0xe0000000 0x100000>;
};
};
/include/ "mpc8548-post.dtsi"
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* MPC8548CDS (36-bit address map) Device Tree Source
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
*/
/include/ "mpc8548.dtsi"
/ {
model = "fsl,MPC8548CDS";
compatible = "fsl,MPC8548CDS";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
soc: soc8548@fe0000000 {
ranges = <0x0 0xf 0xe0000000 0x100000>;
};
};
/include/ "mpc8548-post.dtsi"
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1020 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2019 NXP
*/
&soc {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,p1020-immr", "simple-bus";
bus-frequency = <0x0>;
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <4>;
reg = <0x40000 0x40000>;
compatible = "fsl,mpic";
device_type = "open-pic";
big-endian;
single-cpu-affinity;
last-interrupt-source = <255>;
};
};
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1020 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2019 NXP
*/
/dts-v1/;
/include/ "e500v2_power_isa.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: PowerPC,P1020@0 {
device_type = "cpu";
reg = <0>;
};
cpu1: PowerPC,P1020@1 {
device_type = "cpu";
reg = <1>;
};
};
};
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1020RDB-PC Device Tree Source
*
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
*/
/include/ "p1020.dtsi"
/ {
model = "fsl,P1020RDB-PC";
compatible = "fsl,P1020RDB-PC";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
};
};
/include/ "p1020-post.dtsi"
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1020RDB-PC (36-bit address map) Device Tree Source
*
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
*/
/include/ "p1020.dtsi"
/ {
model = "fsl,P1020RDB-PC";
compatible = "fsl,P1020RDB-PC";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
soc: soc@fffe00000 {
ranges = <0x0 0xf 0xffe00000 0x100000>;
};
};
/include/ "p1020-post.dtsi"
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P1020RDB-PD Device Tree Source
*
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
*/
/include/ "p1020.dtsi"
/ {
model = "fsl,P1020RDB-PD";
compatible = "fsl,P1020RDB-PD";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
};
};
/include/ "p1020-post.dtsi"
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P2020 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2019 NXP
*/
&soc {
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "fsl,p2020-immr", "simple-bus";
bus-frequency = <0x0>;
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <4>;
reg = <0x40000 0x40000>;
compatible = "fsl,mpic";
device_type = "open-pic";
big-endian;
single-cpu-affinity;
last-interrupt-source = <255>;
};
};
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P2020 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2019 NXP
*/
/dts-v1/;
/include/ "e500v2_power_isa.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: PowerPC,P2020@0 {
device_type = "cpu";
reg = <0>;
};
cpu1: PowerPC,P2020@1 {
device_type = "cpu";
reg = <1>;
};
};
};
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P2020RDB-PC Device Tree Source
*
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
*/
/include/ "p2020.dtsi"
/ {
model = "fsl,P2020RDB-PC";
compatible = "fsl,P2020RDB-PC";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
};
};
/include/ "p2020-post.dtsi"
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P2020RDB-PC (36-bit address map) Device Tree Source
*
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
*/
/include/ "p2020.dtsi"
/ {
model = "fsl,P2020RDB-PC";
compatible = "fsl,P2020RDB-PC";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
soc: soc@fffe00000 {
ranges = <0x0 0xf 0xffe00000 0x100000>;
};
};
/include/ "p2020-post.dtsi"
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P2041 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
*/
/dts-v1/;
/include/ "e500mc_power_isa.dtsi"
/ {
compatible = "fsl,P2041";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: PowerPC,e500mc@0 {
device_type = "cpu";
reg = <0>;
fsl,portid-mapping = <0x80000000>;
};
cpu1: PowerPC,e500mc@1 {
device_type = "cpu";
reg = <1>;
fsl,portid-mapping = <0x40000000>;
};
cpu2: PowerPC,e500mc@2 {
device_type = "cpu";
reg = <2>;
fsl,portid-mapping = <0x20000000>;
};
cpu3: PowerPC,e500mc@3 {
device_type = "cpu";
reg = <3>;
fsl,portid-mapping = <0x10000000>;
};
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <4>;
reg = <0x40000 0x40000>;
compatible = "fsl,mpic", "chrp,open-pic";
device_type = "open-pic";
clock-frequency = <0x0>;
};
};
};
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* P2041RDB Device Tree Source
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
*/
/include/ "p2041.dtsi"
/ {
model = "fsl,P2041RDB";
compatible = "fsl,P2041RDB";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
};
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