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Commit ce4ca2b7 authored by Tom Rini's avatar Tom Rini
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ppc: Remove gdsys strider boards 


These boards have not been converted to CONFIG_DM_MMC, along with other
DM conversions, by the deadline.  Remove them.

Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Signed-off-by: default avatarTom Rini <trini@konsulko.com>
parent ddfb9aef
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arch/powerpc/cpu/mpc83xx/Kconfig
+ 0
− 6
View file @ ce4ca2b7
......@@ -137,12 +137,6 @@ config TARGET_HRCON
select ARCH_MPC8308
select SYS_FSL_ERRATUM_ESDHC111
config TARGET_STRIDER
bool "Support strider"
select ARCH_MPC8308
select SYS_FSL_ERRATUM_ESDHC111
imply CMD_PCA953X
config TARGET_GAZERBEAM
bool "Support gazerbeam"
select ARCH_MPC8308
......
board/gdsys/common/Makefile
+ 0
− 4
View file @ ce4ca2b7
......@@ -7,10 +7,6 @@ obj-$(CONFIG_SYS_FPGA_COMMON) += fpga.o
obj-$(CONFIG_CMD_IOLOOP) += cmd_ioloop.o
obj-$(CONFIG_CONTROLCENTERD) += dp501.o
obj-$(CONFIG_TARGET_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o fanctrl.o
obj-$(CONFIG_TARGET_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o
obj-$(CONFIG_TARGET_STRIDER) += fanctrl.o
obj-$(CONFIG_STRIDER_CON) += osd.o
obj-$(CONFIG_STRIDER_CON_DP) += osd.o
obj-$(CONFIG_TARGET_GAZERBEAM) += osd.o ihs_mdio.o ioep-fpga.o
ifdef CONFIG_OSD
......
board/gdsys/common/adv7611.c deleted 100644 → 0
+ 0
− 180
View file @ ddfb9aef
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2014
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
#include <common.h>
#include <i2c.h>
#define ADV7611_I2C_ADDR 0x4c
#define ADV7611_RDINFO 0x2051
/*
* ADV7611 I2C Addresses in u-boot notation
*/
enum {
CP_I2C_ADDR = 0x22,
DPLL_I2C_ADDR = 0x26,
KSV_I2C_ADDR = 0x32,
HDMI_I2C_ADDR = 0x34,
EDID_I2C_ADDR = 0x36,
INFOFRAME_I2C_ADDR = 0x3e,
CEC_I2C_ADDR = 0x40,
IO_I2C_ADDR = ADV7611_I2C_ADDR,
};
/*
* Global Control Registers
*/
enum {
IO_RD_INFO_MSB = 0xea,
IO_RD_INFO_LSB = 0xeb,
IO_CEC_ADDR = 0xf4,
IO_INFOFRAME_ADDR = 0xf5,
IO_DPLL_ADDR = 0xf8,
IO_KSV_ADDR = 0xf9,
IO_EDID_ADDR = 0xfa,
IO_HDMI_ADDR = 0xfb,
IO_CP_ADDR = 0xfd,
};
int adv7611_i2c[] = CONFIG_SYS_ADV7611_I2C;
int adv7611_probe(unsigned int screen)
{
int old_bus = i2c_get_bus_num();
unsigned int rd_info;
int res = 0;
i2c_set_bus_num(adv7611_i2c[screen]);
rd_info = (i2c_reg_read(IO_I2C_ADDR, IO_RD_INFO_MSB) << 8)
| i2c_reg_read(IO_I2C_ADDR, IO_RD_INFO_LSB);
if (rd_info != ADV7611_RDINFO) {
res = -1;
goto out;
}
/*
* set I2C addresses to default values
*/
i2c_reg_write(IO_I2C_ADDR, IO_CEC_ADDR, CEC_I2C_ADDR << 1);
i2c_reg_write(IO_I2C_ADDR, IO_INFOFRAME_ADDR, INFOFRAME_I2C_ADDR << 1);
i2c_reg_write(IO_I2C_ADDR, IO_DPLL_ADDR, DPLL_I2C_ADDR << 1);
i2c_reg_write(IO_I2C_ADDR, IO_KSV_ADDR, KSV_I2C_ADDR << 1);
i2c_reg_write(IO_I2C_ADDR, IO_EDID_ADDR, EDID_I2C_ADDR << 1);
i2c_reg_write(IO_I2C_ADDR, IO_HDMI_ADDR, HDMI_I2C_ADDR << 1);
i2c_reg_write(IO_I2C_ADDR, IO_CP_ADDR, CP_I2C_ADDR << 1);
/*
* do magic initialization sequence from
* "ADV7611 Register Settings Recommendations Revision 1.5"
* with most registers undocumented
*/
i2c_reg_write(CP_I2C_ADDR, 0x6c, 0x00);
i2c_reg_write(HDMI_I2C_ADDR, 0x9b, 0x03);
i2c_reg_write(HDMI_I2C_ADDR, 0x6f, 0x08);
i2c_reg_write(HDMI_I2C_ADDR, 0x85, 0x1f);
i2c_reg_write(HDMI_I2C_ADDR, 0x87, 0x70);
i2c_reg_write(HDMI_I2C_ADDR, 0x57, 0xda);
i2c_reg_write(HDMI_I2C_ADDR, 0x58, 0x01);
i2c_reg_write(HDMI_I2C_ADDR, 0x03, 0x98);
i2c_reg_write(HDMI_I2C_ADDR, 0x4c, 0x44);
/*
* IO_REG_02, default 0xf0
*
* INP_COLOR_SPACE (IO, Address 0x02[7:4])
* default: 0b1111 auto
* set to : 0b0001 force RGB (range 0 to 255) input
*
* RGB_OUT (IO, Address 0x02[1])
* default: 0 YPbPr color space output
* set to : 1 RGB color space output
*/
i2c_reg_write(IO_I2C_ADDR, 0x02, 0x12);
/*
* IO_REG_03, default 0x00
*
* OP_FORMAT_SEL (IO, Address 0x03[7:0])
* default: 0x00 8-bit SDR ITU-656 mode
* set to : 0x40 24-bit 4:4:4 SDR mode
*/
i2c_reg_write(IO_I2C_ADDR, 0x03, 0x40);
/*
* IO_REG_05, default 0x2c
*
* AVCODE_INSERT_EN (IO, Address 0x05[2])
* default: 1 insert AV codes into data stream
* set to : 0 do not insert AV codes into data stream
*/
i2c_reg_write(IO_I2C_ADDR, 0x05, 0x28);
/*
* IO_REG_0C, default 0x62
*
* POWER_DOWN (IO, Address 0x0C[5])
* default: 1 chip is powered down
* set to : 0 chip is operational
*/
i2c_reg_write(IO_I2C_ADDR, 0x0c, 0x42);
/*
* IO_REG_15, default 0xbe
*
* TRI_SYNCS (IO, Address 0x15[3)
* TRI_LLC (IO, Address 0x15[2])
* TRI_PIX (IO, Address 0x15[1])
* default: 1 video output pins are tristate
* set to : 0 video output pins are active
*/
i2c_reg_write(IO_I2C_ADDR, 0x15, 0xb0);
/*
* HDMI_REGISTER_02H, default 0xff
*
* CLOCK_TERMA_DISABLE (HDMI, Address 0x83[0])
* default: 1 disable termination
* set to : 0 enable termination
* Future options are:
* - use the chips automatic termination control
* - set this manually on cable detect
* but at the moment this seems a safe default.
*/
i2c_reg_write(HDMI_I2C_ADDR, 0x83, 0xfe);
/*
* HDMI_CP_CNTRL_1, default 0x01
*
* HDMI_FRUN_EN (CP, Address 0xBA[0])
* default: 1 Enable the free run feature in HDMI mode
* set to : 0 Disable the free run feature in HDMI mode
*/
i2c_reg_write(CP_I2C_ADDR, 0xba, 0x00);
/*
* INT1_CONFIGURATION, default 0x20
*
* INTRQ_DUR_SEL[1:0] (IO, Address 0x40[7:6])
* default: 00 Interrupt signal is active for 4 Xtal periods
* set to : 11 Active until cleared
*
* INTRQ_OP_SEL[1:0] (IO, Address 0x40[1:0])
* default: 00 Open drain
* set to : 10 Drives high when active
*/
i2c_reg_write(IO_I2C_ADDR, 0x40, 0xc2);
out:
i2c_set_bus_num(old_bus);
return res;
}
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
board/gdsys/common/adv7611.h deleted 100644 → 0
+ 0
− 12
View file @ ddfb9aef
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2014
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
#ifndef _ADV7611_H_
#define _ADV7611_H_
int adv7611_probe(unsigned int screen);
#endif
board/gdsys/common/ch7301.c deleted 100644 → 0
+ 0
− 67
View file @ ddfb9aef
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2014
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
/* Chrontel CH7301C DVI Transmitter */
#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
#include <common.h>
#include <asm/io.h>
#include <errno.h>
#include <i2c.h>
#define CH7301_I2C_ADDR 0x75
enum {
CH7301_CM = 0x1c, /* Clock Mode Register */
CH7301_IC = 0x1d, /* Input Clock Register */
CH7301_GPIO = 0x1e, /* GPIO Control Register */
CH7301_IDF = 0x1f, /* Input Data Format Register */
CH7301_CD = 0x20, /* Connection Detect Register */
CH7301_DC = 0x21, /* DAC Control Register */
CH7301_HPD = 0x23, /* Hot Plug Detection Register */
CH7301_TCTL = 0x31, /* DVI Control Input Register */
CH7301_TPCP = 0x33, /* DVI PLL Charge Pump Ctrl Register */
CH7301_TPD = 0x34, /* DVI PLL Divide Register */
CH7301_TPVT = 0x35, /* DVI PLL Supply Control Register */
CH7301_TPF = 0x36, /* DVI PLL Filter Register */
CH7301_TCT = 0x37, /* DVI Clock Test Register */
CH7301_TSTP = 0x48, /* Test Pattern Register */
CH7301_PM = 0x49, /* Power Management register */
CH7301_VID = 0x4a, /* Version ID Register */
CH7301_DID = 0x4b, /* Device ID Register */
CH7301_DSP = 0x56, /* DVI Sync polarity Register */
};
int ch7301_i2c[] = CONFIG_SYS_CH7301_I2C;
int ch7301_probe(unsigned screen, bool power)
{
u8 value;
i2c_set_bus_num(ch7301_i2c[screen]);
if (i2c_probe(CH7301_I2C_ADDR))
return -1;
value = i2c_reg_read(CH7301_I2C_ADDR, CH7301_DID);
if (value != 0x17)
return -1;
if (power) {
i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPCP, 0x08);
i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPD, 0x16);
i2c_reg_write(CH7301_I2C_ADDR, CH7301_TPF, 0x60);
i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x09);
i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0xc0);
} else {
i2c_reg_write(CH7301_I2C_ADDR, CH7301_DC, 0x00);
i2c_reg_write(CH7301_I2C_ADDR, CH7301_PM, 0x01);
}
return 0;
}
#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
board/gdsys/common/ch7301.h deleted 100644 → 0
+ 0
− 12
View file @ ddfb9aef
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2014
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
#ifndef _CH7301_H_
#define _CH7301_H_
int ch7301_probe(unsigned screen, bool power);
#endif
board/gdsys/mpc8308/Kconfig
+ 1
− 20
View file @ ce4ca2b7
......@@ -52,25 +52,6 @@ config GDSYS_LEGACY_DRIVERS
endif
if TARGET_STRIDER
config SYS_BOARD
default "mpc8308"
config SYS_VENDOR
default "gdsys"
config SYS_CONFIG_NAME
default "strider"
config GDSYS_LEGACY_OSD_CMDS
default y
config GDSYS_LEGACY_DRIVERS
default y
endif
if TARGET_GAZERBEAM
config SYS_BOARD
......@@ -92,7 +73,7 @@ config GDSYS_LEGACY_OSD_CMDS
default y
endif
if TARGET_HRCON || TARGET_STRIDER || TARGET_GAZERBEAM
if TARGET_HRCON || TARGET_GAZERBEAM
choice
prompt "FPGA flavor selection"
......
board/gdsys/mpc8308/MAINTAINERS
+ 0
− 6
View file @ ce4ca2b7
......@@ -5,10 +5,4 @@ F: board/gdsys/mpc8308/
F: include/configs/hrcon.h
F: configs/hrcon_defconfig
F: configs/hrcon_dh_defconfig
F: include/configs/strider.h
F: configs/strider_defconfig
F: configs/strider_cpu_defconfig
F: configs/strider_cpu_dp_defconfig
F: configs/strider_con_defconfig
F: configs/strider_con_dp_defconfig
F: configs/gazerbeam_defconfig
board/gdsys/mpc8308/Makefile
+ 0
− 1
View file @ ce4ca2b7
......@@ -5,5 +5,4 @@
obj-y := mpc8308.o sdram.o
obj-$(CONFIG_TARGET_HRCON) += hrcon.o
obj-$(CONFIG_TARGET_STRIDER) += strider.o
obj-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.o
board/gdsys/mpc8308/strider.c deleted 100644 → 0
+ 0
− 559
View file @ ddfb9aef
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2014
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*/
#include <common.h>
#include <env.h>
#include <flash.h>
#include <hwconfig.h>
#include <i2c.h>
#include <init.h>
#include <spi.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <pci.h>
#include <mpc83xx.h>
#include <fsl_esdhc.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_mpc83xx_serdes.h>
#include "mpc8308.h"
#include <gdsys_fpga.h>
#include "../common/adv7611.h"
#include "../common/ch7301.h"
#include "../common/dp501.h"
#include "../common/ioep-fpga.h"
#include "../common/mclink.h"
#include "../common/osd.h"
#include "../common/phy.h"
#include "../common/fanctrl.h"
#include <pca953x.h>
#include <pca9698.h>
#include <miiphy.h>
#define MAX_MUX_CHANNELS 2
enum {
MCFPGA_DONE = 1 << 0,
MCFPGA_INIT_N = 1 << 1,
MCFPGA_PROGRAM_N = 1 << 2,
MCFPGA_UPDATE_ENABLE_N = 1 << 3,
MCFPGA_RESET_N = 1 << 4,
};
enum {
GPIO_MDC = 1 << 14,
GPIO_MDIO = 1 << 15,
};
uint mclink_fpgacount;
struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
struct {
u8 bus;
u8 addr;
} strider_fans[] = CONFIG_STRIDER_FANS;
int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
{
int res;
switch (fpga) {
case 0:
out_le16(reg, data);
break;
default:
res = mclink_send(fpga - 1, regoff, data);
if (res < 0) {
printf("mclink_send reg %02lx data %04x returned %d\n",
regoff, data, res);
return res;
}
break;
}
return 0;
}
int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
{
int res;
switch (fpga) {
case 0:
*data = in_le16(reg);
break;
default:
if (fpga > mclink_fpgacount)
return -EINVAL;
res = mclink_receive(fpga - 1, regoff, data);
if (res < 0) {
printf("mclink_receive reg %02lx returned %d\n",
regoff, res);
return res;
}
}
return 0;
}
int checkboard(void)
{
char *s = env_get("serial#");
bool hw_type_cat = pca9698_get_value(0x20, 18);
puts("Board: ");
printf("Strider %s", hw_type_cat ? "CAT" : "Fiber");
if (s) {
puts(", serial# ");
puts(s);
}
puts("\n");
return 0;
}
int last_stage_init(void)
{
int slaves;
uint k;
uint mux_ch;
uchar mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };
#ifdef CONFIG_STRIDER_CPU
uchar mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };
#endif
bool hw_type_cat = pca9698_get_value(0x20, 18);
#ifdef CONFIG_STRIDER_CON_DP
bool is_dh = pca9698_get_value(0x20, 25);
#endif
bool ch0_sgmii2_present;
/* Turn on Analog Devices ADV7611 */
pca9698_direction_output(0x20, 8, 0);
/* Turn on Parade DP501 */
pca9698_direction_output(0x20, 10, 1);
pca9698_direction_output(0x20, 11, 1);
ch0_sgmii2_present = !pca9698_get_value(0x20, 37);
/* wait for FPGA done, then reset FPGA */
for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) {
uint ctr = 0;
uchar *mclink_controllers = mclink_controllers_dvi;
#ifdef CONFIG_STRIDER_CPU
if (i2c_probe(mclink_controllers[k])) {
mclink_controllers = mclink_controllers_dp;
if (i2c_probe(mclink_controllers[k]))
continue;
}
#else
if (i2c_probe(mclink_controllers[k]))
continue;
#endif
while (!(pca953x_get_val(mclink_controllers[k])
& MCFPGA_DONE)) {
mdelay(100);
if (ctr++ > 5) {
printf("no done for mclink_controller %d\n", k);
break;
}
}
pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);
pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);
udelay(10);
pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N,
MCFPGA_RESET_N);
}
if (hw_type_cat) {
int retval;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);
mdiodev->read = bb_miiphy_read;
mdiodev->write = bb_miiphy_write;
retval = mdio_register(mdiodev);
if (retval < 0)
return retval;
for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {
if ((mux_ch == 1) && !ch0_sgmii2_present)
continue;
setup_88e1514(bb_miiphy_buses[0].name, mux_ch);
}
}
/* give slave-PLLs and Parade DP501 some time to be up and running */
mdelay(500);
mclink_fpgacount = CONFIG_SYS_MCLINK_MAX;
slaves = mclink_probe();
mclink_fpgacount = 0;
ioep_fpga_print_info(0);
if (!adv7611_probe(0))
printf(" Advantiv ADV7611 HDMI Receiver\n");
#ifdef CONFIG_STRIDER_CON
if (ioep_fpga_has_osd(0))
osd_probe(0);
#endif
#ifdef CONFIG_STRIDER_CON_DP
if (ioep_fpga_has_osd(0)) {
osd_probe(0);
if (is_dh)
osd_probe(4);
}
#endif
#ifdef CONFIG_STRIDER_CPU
ch7301_probe(0, false);
dp501_probe(0, false);
#endif
if (slaves <= 0)
return 0;
mclink_fpgacount = slaves;
#ifdef CONFIG_STRIDER_CPU
/* get ADV7611 out of reset, power up DP501, give some time to wakeup */
for (k = 1; k <= slaves; ++k)
FPGA_SET_REG(k, extended_control, 0x10); /* enable video */
mdelay(500);
#endif
for (k = 1; k <= slaves; ++k) {
ioep_fpga_print_info(k);
#ifdef CONFIG_STRIDER_CON
if (ioep_fpga_has_osd(k))
osd_probe(k);
#endif
#ifdef CONFIG_STRIDER_CON_DP
if (ioep_fpga_has_osd(k)) {
osd_probe(k);
if (is_dh)
osd_probe(k + 4);
}
#endif
#ifdef CONFIG_STRIDER_CPU
if (!adv7611_probe(k))
printf(" Advantiv ADV7611 HDMI Receiver\n");
ch7301_probe(k, false);
dp501_probe(k, false);
#endif
if (hw_type_cat) {
int retval;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
strncpy(mdiodev->name, bb_miiphy_buses[k].name,
MDIO_NAME_LEN);
mdiodev->read = bb_miiphy_read;
mdiodev->write = bb_miiphy_write;
retval = mdio_register(mdiodev);
if (retval < 0)
return retval;
setup_88e1514(bb_miiphy_buses[k].name, 0);
}
}
for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) {
i2c_set_bus_num(strider_fans[k].bus);
init_fan_controller(strider_fans[k].addr);
}
return 0;
}
/*
* provide access to fpga gpios (for I2C bitbang)
* (these may look all too simple but make iocon.h much more readable)
*/
void fpga_gpio_set(uint bus, int pin)
{
FPGA_SET_REG(bus, gpio.set, pin);
}
void fpga_gpio_clear(uint bus, int pin)
{
FPGA_SET_REG(bus, gpio.clear, pin);
}
int fpga_gpio_get(uint bus, int pin)
{
u16 val;
FPGA_GET_REG(bus, gpio.read, &val);
return val & pin;
}
#ifdef CONFIG_STRIDER_CON_DP
void fpga_control_set(uint bus, int pin)
{
u16 val;
FPGA_GET_REG(bus, control, &val);
FPGA_SET_REG(bus, control, val | pin);
}
void fpga_control_clear(uint bus, int pin)
{
u16 val;
FPGA_GET_REG(bus, control, &val);
FPGA_SET_REG(bus, control, val & ~pin);
}
#endif
void mpc8308_init(void)
{
pca9698_direction_output(0x20, 26, 1);
}
void mpc8308_set_fpga_reset(uint state)
{
pca9698_set_value(0x20, 26, state ? 0 : 1);
}
void mpc8308_setup_hw(void)
{
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
/*
* set "startup-finished"-gpios
*/
setbits_be32(&immr->gpio[0].dir, BIT(31 - 11) | BIT(31 - 12));
setbits_gpio0_out(BIT(31 - 12));
}
int mpc8308_get_fpga_done(uint fpga)
{
return pca9698_get_value(0x20, 20);
}
#ifdef CONFIG_FSL_ESDHC
int board_mmc_init(struct bd_info *bd)
{
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
sysconf83xx_t *sysconf = &immr->sysconf;
/* Enable cache snooping in eSDHC system configuration register */
out_be32(&sysconf->sdhccr, 0x02000000);
return fsl_esdhc_mmc_init(bd);
}
#endif
static struct pci_region pcie_regions_0[] = {
{
.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
.size = CONFIG_SYS_PCIE1_MEM_SIZE,
.flags = PCI_REGION_MEM,
},
{
.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
.size = CONFIG_SYS_PCIE1_IO_SIZE,
.flags = PCI_REGION_IO,
},
};
void pci_init_board(void)
{
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
sysconf83xx_t *sysconf = &immr->sysconf;
law83xx_t *pcie_law = sysconf->pcielaw;
struct pci_region *pcie_reg[] = { pcie_regions_0 };
fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
/* Deassert the resets in the control register */
out_be32(&sysconf->pecr1, 0xE0008000);
udelay(2000);
/* Configure PCI Express Local Access Windows */
out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
mpc83xx_pcie_init(1, pcie_reg);
}
ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
{
info->portwidth = FLASH_CFI_16BIT;
info->chipwidth = FLASH_CFI_BY16;
info->interface = FLASH_CFI_X16;
return 1;
}
#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
ft_cpu_setup(blob, bd);
fsl_fdt_fixup_dr_usb(blob, bd);
fdt_fixup_esdhc(blob, bd);
return 0;
}
#endif
/*
* FPGA MII bitbang implementation
*/
struct fpga_mii {
uint fpga;
int mdio;
} fpga_mii[] = {
{ 0, 1},
{ 1, 1},
{ 2, 1},
{ 3, 1},
};
static int mii_dummy_init(struct bb_miiphy_bus *bus)
{
return 0;
}
static int mii_mdio_active(struct bb_miiphy_bus *bus)
{
struct fpga_mii *fpga_mii = bus->priv;
if (fpga_mii->mdio)
FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
else
FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
return 0;
}
static int mii_mdio_tristate(struct bb_miiphy_bus *bus)
{
struct fpga_mii *fpga_mii = bus->priv;
FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
return 0;
}
static int mii_set_mdio(struct bb_miiphy_bus *bus, int v)
{
struct fpga_mii *fpga_mii = bus->priv;
if (v)
FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDIO);
else
FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDIO);
fpga_mii->mdio = v;
return 0;
}
static int mii_get_mdio(struct bb_miiphy_bus *bus, int *v)
{
u16 gpio;
struct fpga_mii *fpga_mii = bus->priv;
FPGA_GET_REG(fpga_mii->fpga, gpio.read, &gpio);
*v = ((gpio & GPIO_MDIO) != 0);
return 0;
}
static int mii_set_mdc(struct bb_miiphy_bus *bus, int v)
{
struct fpga_mii *fpga_mii = bus->priv;
if (v)
FPGA_SET_REG(fpga_mii->fpga, gpio.set, GPIO_MDC);
else
FPGA_SET_REG(fpga_mii->fpga, gpio.clear, GPIO_MDC);
return 0;
}
static int mii_delay(struct bb_miiphy_bus *bus)
{
udelay(1);
return 0;
}
struct bb_miiphy_bus bb_miiphy_buses[] = {
{
.name = "board0",
.init = mii_dummy_init,
.mdio_active = mii_mdio_active,
.mdio_tristate = mii_mdio_tristate,
.set_mdio = mii_set_mdio,
.get_mdio = mii_get_mdio,
.set_mdc = mii_set_mdc,
.delay = mii_delay,
.priv = &fpga_mii[0],
},
{
.name = "board1",
.init = mii_dummy_init,
.mdio_active = mii_mdio_active,
.mdio_tristate = mii_mdio_tristate,
.set_mdio = mii_set_mdio,
.get_mdio = mii_get_mdio,
.set_mdc = mii_set_mdc,
.delay = mii_delay,
.priv = &fpga_mii[1],
},
{
.name = "board2",
.init = mii_dummy_init,
.mdio_active = mii_mdio_active,
.mdio_tristate = mii_mdio_tristate,
.set_mdio = mii_set_mdio,
.get_mdio = mii_get_mdio,
.set_mdc = mii_set_mdc,
.delay = mii_delay,
.priv = &fpga_mii[2],
},
{
.name = "board3",
.init = mii_dummy_init,
.mdio_active = mii_mdio_active,
.mdio_tristate = mii_mdio_tristate,
.set_mdio = mii_set_mdio,
.get_mdio = mii_get_mdio,
.set_mdc = mii_set_mdc,
.delay = mii_delay,
.priv = &fpga_mii[3],
},
};
int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
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CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_SYS_MEMTEST_START=0x00001000
CONFIG_SYS_MEMTEST_END=0x07f00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_IDENT_STRING=" strider con 0.01"
CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
CONFIG_SYSTEM_PLL_VCO_DIV_2=y
CONFIG_SYSTEM_PLL_FACTOR_4_1=y
CONFIG_CORE_PLL_RATIO_3_1=y
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
CONFIG_TSEC2_MODE_RGMII=y
CONFIG_BAT0=y
CONFIG_BAT0_NAME="DDR"
CONFIG_BAT0_BASE=0x00000000
CONFIG_BAT0_LENGTH_128_MBYTES=y
CONFIG_BAT0_ACCESS_RW=y
CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
CONFIG_BAT0_USER_MODE_VALID=y
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
CONFIG_BAT1=y
CONFIG_BAT1_NAME="IMMRBAR"
CONFIG_BAT1_BASE=0xE0000000
CONFIG_BAT1_LENGTH_8_MBYTES=y
CONFIG_BAT1_ACCESS_RW=y
CONFIG_BAT1_ICACHE_INHIBITED=y
CONFIG_BAT1_ICACHE_GUARDED=y
CONFIG_BAT1_DCACHE_INHIBITED=y
CONFIG_BAT1_DCACHE_GUARDED=y
CONFIG_BAT1_USER_MODE_VALID=y
CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
CONFIG_BAT2=y
CONFIG_BAT2_NAME="FLASH"
CONFIG_BAT2_BASE=0xFE000000
CONFIG_BAT2_LENGTH_8_MBYTES=y
CONFIG_BAT2_ACCESS_RW=y
CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT2_DCACHE_INHIBITED=y
CONFIG_BAT2_DCACHE_GUARDED=y
CONFIG_BAT2_USER_MODE_VALID=y
CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
CONFIG_BAT3=y
CONFIG_BAT3_NAME="STACK_IN_DCACHE"
CONFIG_BAT3_BASE=0xE6000000
CONFIG_BAT3_ACCESS_RW=y
CONFIG_BAT3_USER_MODE_VALID=y
CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
CONFIG_LBLAW0=y
CONFIG_LBLAW0_BASE=0xFE000000
CONFIG_LBLAW0_NAME="FLASH"
CONFIG_LBLAW0_LENGTH_8_MBYTES=y
CONFIG_LBLAW1=y
CONFIG_LBLAW1_BASE=0xE0600000
CONFIG_LBLAW1_NAME="FPGA0"
CONFIG_LBLAW1_LENGTH_1_MBYTES=y
CONFIG_ELBC_BR0_OR0=y
CONFIG_BR0_OR0_NAME="FLASH"
CONFIG_BR0_OR0_BASE=0xFE000000
CONFIG_BR0_PORTSIZE_16BIT=y
CONFIG_OR0_AM_8_MBYTES=y
CONFIG_OR0_XAM_SET=y
CONFIG_OR0_SCY_15=y
CONFIG_OR0_CSNT_EARLIER=y
CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
CONFIG_OR0_XACS_EXTENDED=y
CONFIG_OR0_TRLX_RELAXED=y
CONFIG_OR0_EHTR_8_CYCLE=y
CONFIG_ELBC_BR1_OR1=y
CONFIG_BR1_OR1_NAME="FPGA"
CONFIG_BR1_OR1_BASE=0xE0600000
CONFIG_BR1_PORTSIZE_16BIT=y
CONFIG_OR1_AM_1_MBYTES=y
CONFIG_OR1_XAM_SET=y
CONFIG_OR1_SCY_5=y
CONFIG_OR1_CSNT_EARLIER=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_DPM=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
CONFIG_SICR_IEEE1588_A_GPIO=y
CONFIG_SICR_GTM_GPIO=y
CONFIG_SICR_ETSEC2_GPIO=y
CONFIG_SICR_GPIOSEL_IEEE1588=y
CONFIG_SICR_TMSOBI1_2_5_V=y
CONFIG_SICR_TMSOBI2_2_5_V=y
CONFIG_ACR_PIPE_DEP_4=y
CONFIG_ACR_RPTCNT_4=y
CONFIG_SPCR_TSECEP_3=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_2=y
CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON"
CONFIG_BOOTDELAY=5
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_FPGAD=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0xFE060000
CONFIG_ENV_ADDR_REDUND=0xFE070000
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_BITBANGMII=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
configs/strider_con_dp_defconfig deleted 100644 → 0
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CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_SYS_MEMTEST_START=0x00001000
CONFIG_SYS_MEMTEST_END=0x07f00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_IDENT_STRING=" strider con dp 0.01"
CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
CONFIG_SYSTEM_PLL_VCO_DIV_2=y
CONFIG_SYSTEM_PLL_FACTOR_4_1=y
CONFIG_CORE_PLL_RATIO_3_1=y
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
CONFIG_TSEC2_MODE_RGMII=y
CONFIG_BAT0=y
CONFIG_BAT0_NAME="DDR"
CONFIG_BAT0_BASE=0x00000000
CONFIG_BAT0_LENGTH_128_MBYTES=y
CONFIG_BAT0_ACCESS_RW=y
CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
CONFIG_BAT0_USER_MODE_VALID=y
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
CONFIG_BAT1=y
CONFIG_BAT1_NAME="IMMRBAR"
CONFIG_BAT1_BASE=0xE0000000
CONFIG_BAT1_LENGTH_8_MBYTES=y
CONFIG_BAT1_ACCESS_RW=y
CONFIG_BAT1_ICACHE_INHIBITED=y
CONFIG_BAT1_ICACHE_GUARDED=y
CONFIG_BAT1_DCACHE_INHIBITED=y
CONFIG_BAT1_DCACHE_GUARDED=y
CONFIG_BAT1_USER_MODE_VALID=y
CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
CONFIG_BAT2=y
CONFIG_BAT2_NAME="FLASH"
CONFIG_BAT2_BASE=0xFE000000
CONFIG_BAT2_LENGTH_8_MBYTES=y
CONFIG_BAT2_ACCESS_RW=y
CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT2_DCACHE_INHIBITED=y
CONFIG_BAT2_DCACHE_GUARDED=y
CONFIG_BAT2_USER_MODE_VALID=y
CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
CONFIG_BAT3=y
CONFIG_BAT3_NAME="STACK_IN_DCACHE"
CONFIG_BAT3_BASE=0xE6000000
CONFIG_BAT3_ACCESS_RW=y
CONFIG_BAT3_USER_MODE_VALID=y
CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
CONFIG_LBLAW0=y
CONFIG_LBLAW0_BASE=0xFE000000
CONFIG_LBLAW0_NAME="FLASH"
CONFIG_LBLAW0_LENGTH_8_MBYTES=y
CONFIG_LBLAW1=y
CONFIG_LBLAW1_BASE=0xE0600000
CONFIG_LBLAW1_NAME="FPGA0"
CONFIG_LBLAW1_LENGTH_1_MBYTES=y
CONFIG_ELBC_BR0_OR0=y
CONFIG_BR0_OR0_NAME="FLASH"
CONFIG_BR0_OR0_BASE=0xFE000000
CONFIG_BR0_PORTSIZE_16BIT=y
CONFIG_OR0_AM_8_MBYTES=y
CONFIG_OR0_XAM_SET=y
CONFIG_OR0_SCY_15=y
CONFIG_OR0_CSNT_EARLIER=y
CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
CONFIG_OR0_XACS_EXTENDED=y
CONFIG_OR0_TRLX_RELAXED=y
CONFIG_OR0_EHTR_8_CYCLE=y
CONFIG_ELBC_BR1_OR1=y
CONFIG_BR1_OR1_NAME="FPGA"
CONFIG_BR1_OR1_BASE=0xE0600000
CONFIG_BR1_PORTSIZE_16BIT=y
CONFIG_OR1_AM_1_MBYTES=y
CONFIG_OR1_XAM_SET=y
CONFIG_OR1_SCY_5=y
CONFIG_OR1_CSNT_EARLIER=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_DPM=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
CONFIG_SICR_IEEE1588_A_GPIO=y
CONFIG_SICR_GTM_GPIO=y
CONFIG_SICR_ETSEC2_GPIO=y
CONFIG_SICR_GPIOSEL_IEEE1588=y
CONFIG_SICR_TMSOBI1_2_5_V=y
CONFIG_SICR_TMSOBI2_2_5_V=y
CONFIG_ACR_PIPE_DEP_4=y
CONFIG_ACR_RPTCNT_4=y
CONFIG_SPCR_TSECEP_3=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_2=y
CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CON_DP"
CONFIG_BOOTDELAY=5
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_FPGAD=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0xFE060000
CONFIG_ENV_ADDR_REDUND=0xFE070000
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_BITBANGMII=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
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View file @ ddfb9aef
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_SYS_MEMTEST_START=0x00001000
CONFIG_SYS_MEMTEST_END=0x07f00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_IDENT_STRING=" strider cpu 0.01"
CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
CONFIG_SYSTEM_PLL_VCO_DIV_2=y
CONFIG_SYSTEM_PLL_FACTOR_4_1=y
CONFIG_CORE_PLL_RATIO_3_1=y
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
CONFIG_TSEC2_MODE_RGMII=y
CONFIG_BAT0=y
CONFIG_BAT0_NAME="DDR"
CONFIG_BAT0_BASE=0x00000000
CONFIG_BAT0_LENGTH_128_MBYTES=y
CONFIG_BAT0_ACCESS_RW=y
CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
CONFIG_BAT0_USER_MODE_VALID=y
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
CONFIG_BAT1=y
CONFIG_BAT1_NAME="IMMRBAR"
CONFIG_BAT1_BASE=0xE0000000
CONFIG_BAT1_LENGTH_8_MBYTES=y
CONFIG_BAT1_ACCESS_RW=y
CONFIG_BAT1_ICACHE_INHIBITED=y
CONFIG_BAT1_ICACHE_GUARDED=y
CONFIG_BAT1_DCACHE_INHIBITED=y
CONFIG_BAT1_DCACHE_GUARDED=y
CONFIG_BAT1_USER_MODE_VALID=y
CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
CONFIG_BAT2=y
CONFIG_BAT2_NAME="FLASH"
CONFIG_BAT2_BASE=0xFE000000
CONFIG_BAT2_LENGTH_8_MBYTES=y
CONFIG_BAT2_ACCESS_RW=y
CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT2_DCACHE_INHIBITED=y
CONFIG_BAT2_DCACHE_GUARDED=y
CONFIG_BAT2_USER_MODE_VALID=y
CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
CONFIG_BAT3=y
CONFIG_BAT3_NAME="STACK_IN_DCACHE"
CONFIG_BAT3_BASE=0xE6000000
CONFIG_BAT3_ACCESS_RW=y
CONFIG_BAT3_USER_MODE_VALID=y
CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
CONFIG_LBLAW0=y
CONFIG_LBLAW0_BASE=0xFE000000
CONFIG_LBLAW0_NAME="FLASH"
CONFIG_LBLAW0_LENGTH_8_MBYTES=y
CONFIG_LBLAW1=y
CONFIG_LBLAW1_BASE=0xE0600000
CONFIG_LBLAW1_NAME="FPGA0"
CONFIG_LBLAW1_LENGTH_1_MBYTES=y
CONFIG_ELBC_BR0_OR0=y
CONFIG_BR0_OR0_NAME="FLASH"
CONFIG_BR0_OR0_BASE=0xFE000000
CONFIG_BR0_PORTSIZE_16BIT=y
CONFIG_OR0_AM_8_MBYTES=y
CONFIG_OR0_XAM_SET=y
CONFIG_OR0_SCY_15=y
CONFIG_OR0_CSNT_EARLIER=y
CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
CONFIG_OR0_XACS_EXTENDED=y
CONFIG_OR0_TRLX_RELAXED=y
CONFIG_OR0_EHTR_8_CYCLE=y
CONFIG_ELBC_BR1_OR1=y
CONFIG_BR1_OR1_NAME="FPGA"
CONFIG_BR1_OR1_BASE=0xE0600000
CONFIG_BR1_PORTSIZE_16BIT=y
CONFIG_OR1_AM_1_MBYTES=y
CONFIG_OR1_XAM_SET=y
CONFIG_OR1_SCY_5=y
CONFIG_OR1_CSNT_EARLIER=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_DPM=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
CONFIG_SICR_IEEE1588_A_GPIO=y
CONFIG_SICR_GTM_GPIO=y
CONFIG_SICR_ETSEC2_GPIO=y
CONFIG_SICR_GPIOSEL_IEEE1588=y
CONFIG_SICR_TMSOBI1_2_5_V=y
CONFIG_SICR_TMSOBI2_2_5_V=y
CONFIG_ACR_PIPE_DEP_4=y
CONFIG_ACR_RPTCNT_4=y
CONFIG_SPCR_TSECEP_3=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_2=y
CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU"
CONFIG_BOOTDELAY=5
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_FPGAD=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0xFE060000
CONFIG_ENV_ADDR_REDUND=0xFE070000
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_BITBANGMII=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
configs/strider_cpu_dp_defconfig deleted 100644 → 0
+ 0
− 146
View file @ ddfb9aef
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_SYS_MEMTEST_START=0x00001000
CONFIG_SYS_MEMTEST_END=0x07f00000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_IDENT_STRING=" strider cpu dp 0.01"
CONFIG_SYS_CLK_FREQ=33333333
CONFIG_MPC83xx=y
CONFIG_TARGET_STRIDER=y
CONFIG_SYSTEM_PLL_VCO_DIV_2=y
CONFIG_SYSTEM_PLL_FACTOR_4_1=y
CONFIG_CORE_PLL_RATIO_3_1=y
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
CONFIG_TSEC2_MODE_RGMII=y
CONFIG_BAT0=y
CONFIG_BAT0_NAME="DDR"
CONFIG_BAT0_BASE=0x00000000
CONFIG_BAT0_LENGTH_128_MBYTES=y
CONFIG_BAT0_ACCESS_RW=y
CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
CONFIG_BAT0_USER_MODE_VALID=y
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
CONFIG_BAT1=y
CONFIG_BAT1_NAME="IMMRBAR"
CONFIG_BAT1_BASE=0xE0000000
CONFIG_BAT1_LENGTH_8_MBYTES=y
CONFIG_BAT1_ACCESS_RW=y
CONFIG_BAT1_ICACHE_INHIBITED=y
CONFIG_BAT1_ICACHE_GUARDED=y
CONFIG_BAT1_DCACHE_INHIBITED=y
CONFIG_BAT1_DCACHE_GUARDED=y
CONFIG_BAT1_USER_MODE_VALID=y
CONFIG_BAT1_SUPERVISOR_MODE_VALID=y
CONFIG_BAT2=y
CONFIG_BAT2_NAME="FLASH"
CONFIG_BAT2_BASE=0xFE000000
CONFIG_BAT2_LENGTH_8_MBYTES=y
CONFIG_BAT2_ACCESS_RW=y
CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT2_DCACHE_INHIBITED=y
CONFIG_BAT2_DCACHE_GUARDED=y
CONFIG_BAT2_USER_MODE_VALID=y
CONFIG_BAT2_SUPERVISOR_MODE_VALID=y
CONFIG_BAT3=y
CONFIG_BAT3_NAME="STACK_IN_DCACHE"
CONFIG_BAT3_BASE=0xE6000000
CONFIG_BAT3_ACCESS_RW=y
CONFIG_BAT3_USER_MODE_VALID=y
CONFIG_BAT3_SUPERVISOR_MODE_VALID=y
CONFIG_LBLAW0=y
CONFIG_LBLAW0_BASE=0xFE000000
CONFIG_LBLAW0_NAME="FLASH"
CONFIG_LBLAW0_LENGTH_8_MBYTES=y
CONFIG_LBLAW1=y
CONFIG_LBLAW1_BASE=0xE0600000
CONFIG_LBLAW1_NAME="FPGA0"
CONFIG_LBLAW1_LENGTH_1_MBYTES=y
CONFIG_ELBC_BR0_OR0=y
CONFIG_BR0_OR0_NAME="FLASH"
CONFIG_BR0_OR0_BASE=0xFE000000
CONFIG_BR0_PORTSIZE_16BIT=y
CONFIG_OR0_AM_8_MBYTES=y
CONFIG_OR0_XAM_SET=y
CONFIG_OR0_SCY_15=y
CONFIG_OR0_CSNT_EARLIER=y
CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
CONFIG_OR0_XACS_EXTENDED=y
CONFIG_OR0_TRLX_RELAXED=y
CONFIG_OR0_EHTR_8_CYCLE=y
CONFIG_ELBC_BR1_OR1=y
CONFIG_BR1_OR1_NAME="FPGA"
CONFIG_BR1_OR1_BASE=0xE0600000
CONFIG_BR1_PORTSIZE_16BIT=y
CONFIG_OR1_AM_1_MBYTES=y
CONFIG_OR1_XAM_SET=y
CONFIG_OR1_SCY_5=y
CONFIG_OR1_CSNT_EARLIER=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_DPM=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
CONFIG_SICR_IEEE1588_A_GPIO=y
CONFIG_SICR_GTM_GPIO=y
CONFIG_SICR_ETSEC2_GPIO=y
CONFIG_SICR_GPIOSEL_IEEE1588=y
CONFIG_SICR_TMSOBI1_2_5_V=y
CONFIG_SICR_TMSOBI2_2_5_V=y
CONFIG_ACR_PIPE_DEP_4=y
CONFIG_ACR_RPTCNT_4=y
CONFIG_SPCR_TSECEP_3=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_2=y
CONFIG_CMD_IOLOOP=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="STRIDER_CPU,STRIDER_CPU_DP"
CONFIG_BOOTDELAY=5
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_STOP_STR=" "
CONFIG_USE_PREBOOT=y
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_LAST_STAGE_INIT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_FPGAD=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_DOS_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0xFE060000
CONFIG_ENV_ADDR_REDUND=0xFE070000
CONFIG_FSL_ESDHC=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_BITBANGMII=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_MII=y
CONFIG_TSEC_ENET=y
CONFIG_CONS_INDEX=2
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y
include/configs/strider.h deleted 100644 → 0
+ 0
− 454
View file @ ddfb9aef
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2014
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
*
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <linux/stringify.h>
/*
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
/*
* SERDES
*/
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1 0xe3000
/*
* DDR Setup
*/
#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
| DDRCDR_PZ_LOZ \
| DDRCDR_NZ_LOZ \
| DDRCDR_ODT \
| DDRCDR_Q_DRN)
/* 0x7b880001 */
/*
* Manually set up DDR parameters
* consist of one chip NT5TU64M16HG from NANYA
*/
#define CONFIG_SYS_DDR_SIZE 128 /* MB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| CSCONFIG_ODT_RD_NEVER \
| CSCONFIG_ODT_WR_ONLY_CURRENT \
| CSCONFIG_BANK_BIT_3 \
| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
/* 0x80010102 */
#define CONFIG_SYS_DDR_TIMING_3 0
#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
| (0 << TIMING_CFG0_WRT_SHIFT) \
| (0 << TIMING_CFG0_RRT_SHIFT) \
| (0 << TIMING_CFG0_WWT_SHIFT) \
| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
/* 0x00260802 */
#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
| (7 << TIMING_CFG1_CASLAT_SHIFT) \
| (9 << TIMING_CFG1_REFREC_SHIFT) \
| (2 << TIMING_CFG1_WRREC_SHIFT) \
| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
| (2 << TIMING_CFG1_WRTORD_SHIFT))
/* 0x26279222 */
#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
| (4 << TIMING_CFG2_CPO_SHIFT) \
| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
/* 0x021848c5 */
#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
/* 0x08240100 */
#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
| SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_DBW_16)
/* 0x43100000 */
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
| (0x0242 << SDRAM_MODE_SD_SHIFT))
/* ODT 150ohm CL=4, AL=0 on SDRAM */
#define CONFIG_SYS_DDR_MODE2 0x00000000
/*
* Memory test
*/
/*
* The reserved memory
*/
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/*
* Initial RAM Base Address Setup
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/*
* FLASH on the Local Bus
*/
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_FLASH_CFI_LEGACY
#define CONFIG_SYS_FLASH_LEGACY_512Kx16
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 135
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_SYS_FPGA_DONE(k) 0x0010
#define CONFIG_SYS_FPGA_COUNT 1
#define CONFIG_SYS_MCLINK_MAX 3
#define CONFIG_SYS_FPGA_PTR \
{ (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
#define CONFIG_SYS_FPGA_NO_RFL_HI
/*
* Serial Port
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
/* Pass open firmware flat tree */
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED 400000
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
#define CONFIG_PCA953X /* NXP PCA9554 */
#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \
{0x3c, 8}, {0x3d, 8}, {0x3e, 8} }
#define CONFIG_PCA9698 /* NXP PCA9698 */
#define CONFIG_SYS_I2C_IHS
#define CONFIG_SYS_I2C_IHS_CH0
#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
#define CONFIG_SYS_I2C_IHS_CH1
#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
#define CONFIG_SYS_I2C_IHS_CH2
#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
#define CONFIG_SYS_I2C_IHS_CH3
#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
#ifdef CONFIG_STRIDER_CON_DP
#define CONFIG_SYS_I2C_IHS_DUAL
#define CONFIG_SYS_I2C_IHS_CH0_1
#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
#define CONFIG_SYS_I2C_IHS_CH1_1
#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
#define CONFIG_SYS_I2C_IHS_CH2_1
#define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
#define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
#define CONFIG_SYS_I2C_IHS_CH3_1
#define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
#define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
#endif
/*
* Software (bit-bang) I2C driver configuration
*/
#define CONFIG_SYS_I2C_SOFT
#define CONFIG_SOFT_I2C_READ_REPEATED_START
#define CONFIG_SYS_I2C_SOFT_SPEED 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
#define I2C_SOFT_DECLARATIONS2
#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
#define I2C_SOFT_DECLARATIONS3
#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
#define I2C_SOFT_DECLARATIONS4
#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
#if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP)
#define I2C_SOFT_DECLARATIONS5
#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
#define I2C_SOFT_DECLARATIONS6
#define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
#define I2C_SOFT_DECLARATIONS7
#define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
#define I2C_SOFT_DECLARATIONS8
#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
#endif
#ifdef CONFIG_STRIDER_CON_DP
#define I2C_SOFT_DECLARATIONS9
#define CONFIG_SYS_I2C_SOFT_SPEED_9 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F
#define I2C_SOFT_DECLARATIONS10
#define CONFIG_SYS_I2C_SOFT_SPEED_10 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F
#define I2C_SOFT_DECLARATIONS11
#define CONFIG_SYS_I2C_SOFT_SPEED_11 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F
#define I2C_SOFT_DECLARATIONS12
#define CONFIG_SYS_I2C_SOFT_SPEED_12 50000
#define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F
#endif
#ifdef CONFIG_STRIDER_CON
#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
#define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8}
#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
#define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
{12, 0x4c} }
#elif defined(CONFIG_STRIDER_CON_DP)
#define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20}
#define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7}
#define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7}
#define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
#define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \
{12, 0x4c} }
#elif defined(CONFIG_STRIDER_CPU_DP)
#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
#define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
#define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \
{8, 0x4c} }
#else
#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4}
#define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4}
#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
#define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \
{4, 0x18} }
#endif
#ifndef __ASSEMBLY__
void fpga_gpio_set(unsigned int bus, int pin);
void fpga_gpio_clear(unsigned int bus, int pin);
int fpga_gpio_get(unsigned int bus, int pin);
void fpga_control_set(unsigned int bus, int pin);
void fpga_control_clear(unsigned int bus, int pin);
#endif
#ifdef CONFIG_STRIDER_CON
#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040)
#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020)
#define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \
(I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR)
#elif defined(CONFIG_STRIDER_CON_DP)
#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
#define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4)
#else
#define I2C_SDA_GPIO 0x0040
#define I2C_SCL_GPIO 0x0020
#define I2C_FPGA_IDX I2C_ADAP_HWNR
#endif
#ifdef CONFIG_STRIDER_CON_DP
#define I2C_ACTIVE \
do { \
if (I2C_ADAP_HWNR > 7) \
fpga_control_set(I2C_FPGA_IDX, 0x0004); \
else \
fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
} while (0)
#else
#define I2C_ACTIVE { }
#endif
#define I2C_TRISTATE { }
#define I2C_READ \
(fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
#define I2C_SDA(bit) \
do { \
if (bit) \
fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
else \
fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
} while (0)
#define I2C_SCL(bit) \
do { \
if (bit) \
fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
else \
fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
} while (0)
#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
/*
* Software (bit-bang) MII driver configuration
*/
#define CONFIG_BITBANGMII_MULTI
/*
* OSD Setup
*/
#define CONFIG_SYS_OSD_SCREENS 1
#define CONFIG_SYS_DP501_DIFFERENTIAL
#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
#ifdef CONFIG_STRIDER_CON_DP
#define CONFIG_SYS_OSD_DH
#endif
/*
* General PCI
* Addresses are mapped 1-1.
*/
#define CONFIG_SYS_PCIE1_BASE 0xA0000000
#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
/* enable PCIE clock */
#define CONFIG_SYS_SCCR_PCIEXP1CM 1
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCIE
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
/*
* TSEC
*/
#define CONFIG_SYS_TSEC1_OFFSET 0x24000
#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
/*
* TSEC ethernet configuration
*/
#define CONFIG_TSEC1
#define CONFIG_TSEC1_NAME "eTSEC0"
#define TSEC1_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC1_FLAGS 0
/* Options are: eTSEC[0-1] */
#define CONFIG_ETHPRIME "eTSEC0"
/*
* Environment
*/
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
/*
* Environment Configuration
*/
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#endif
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
#define CONFIG_HOSTNAME "hrcon"
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS1\0" \
"u-boot=u-boot.bin\0" \
"kernel_addr=1000000\0" \
"fdt_addr=C00000\0" \
"fdtfile=hrcon.dtb\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
" +${filesize};cp.b ${fileaddr} " \
__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
"upd=run load update\0" \
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp ${kernel_addr} $bootfile;" \
"tftp ${fdt_addr} $fdtfile;" \
"bootm ${kernel_addr} - ${fdt_addr}"
#define CONFIG_MMCBOOTCOMMAND \
"setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \
"console=$consoledev,$baudrate $othbootargs;" \
"ext2load mmc 0:2 ${kernel_addr} $bootfile;" \
"ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \
"bootm ${kernel_addr} - ${fdt_addr}"
#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND
#endif /* __CONFIG_H */
include/gdsys_fpga.h
+ 1
− 64
View file @ ce4ca2b7
......@@ -88,7 +88,7 @@ struct ihs_fpga {
};
#endif
#if defined(CONFIG_TARGET_HRCON) || defined(CONFIG_STRIDER_CON_DP)
#if defined(CONFIG_TARGET_HRCON)
struct ihs_fpga {
u16 reflection_low; /* 0x0000 */
u16 versions; /* 0x0002 */
......@@ -134,67 +134,4 @@ struct ihs_fpga {
};
#endif
#ifdef CONFIG_STRIDER_CPU
struct ihs_fpga {
u16 reflection_low; /* 0x0000 */
u16 versions; /* 0x0002 */
u16 fpga_version; /* 0x0004 */
u16 fpga_features; /* 0x0006 */
u16 reserved_0[1]; /* 0x0008 */
u16 top_interrupt; /* 0x000a */
u16 reserved_1[3]; /* 0x000c */
u16 extended_control; /* 0x0012 */
struct ihs_gpio gpio; /* 0x0014 */
u16 mpc3w_control; /* 0x001a */
u16 reserved_2[2]; /* 0x001c */
struct ihs_io_ep ep; /* 0x0020 */
u16 reserved_3[9]; /* 0x002e */
u16 mc_int; /* 0x0040 */
u16 mc_int_en; /* 0x0042 */
u16 mc_status; /* 0x0044 */
u16 mc_control; /* 0x0046 */
u16 mc_tx_data; /* 0x0048 */
u16 mc_tx_address; /* 0x004a */
u16 mc_tx_cmd; /* 0x004c */
u16 mc_res; /* 0x004e */
u16 mc_rx_cmd_status; /* 0x0050 */
u16 mc_rx_data; /* 0x0052 */
u16 reserved_4[62]; /* 0x0054 */
struct ihs_i2c i2c0; /* 0x00d0 */
};
#endif
#ifdef CONFIG_STRIDER_CON
struct ihs_fpga {
u16 reflection_low; /* 0x0000 */
u16 versions; /* 0x0002 */
u16 fpga_version; /* 0x0004 */
u16 fpga_features; /* 0x0006 */
u16 reserved_0[1]; /* 0x0008 */
u16 top_interrupt; /* 0x000a */
u16 reserved_1[4]; /* 0x000c */
struct ihs_gpio gpio; /* 0x0014 */
u16 mpc3w_control; /* 0x001a */
u16 reserved_2[2]; /* 0x001c */
struct ihs_io_ep ep; /* 0x0020 */
u16 reserved_3[9]; /* 0x002e */
struct ihs_i2c i2c0; /* 0x0040 */
u16 reserved_4[10]; /* 0x004c */
u16 mc_int; /* 0x0060 */
u16 mc_int_en; /* 0x0062 */
u16 mc_status; /* 0x0064 */
u16 mc_control; /* 0x0066 */
u16 mc_tx_data; /* 0x0068 */
u16 mc_tx_address; /* 0x006a */
u16 mc_tx_cmd; /* 0x006c */
u16 mc_res; /* 0x006e */
u16 mc_rx_cmd_status; /* 0x0070 */
u16 mc_rx_data; /* 0x0072 */
u16 reserved_5[70]; /* 0x0074 */
struct ihs_osd osd0; /* 0x0100 */
u16 reserved_6[889]; /* 0x010e */
u16 videomem0[2048]; /* 0x0800 */
};
#endif
#endif
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