- Oct 24, 2022
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Correct pointer dereferencing check to be more consistent. Eliminate the below smatch warning: drivers/mmc/mmc.c:3118 mmc_init_device() warn: variable dereferenced before check 'm' (see line 3116) Signed-off-by:
Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> Reviewed-by:
Michal Simek <michal.simek@amd.com> Reviewed-by:
Jaehoon Chung <jh80.chung@samsung.com>
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Unconditionally clearing DTO when RXDR is set leads to spurious timeouts in FIFO mode transfers if events occur in the following order: mask = dwmci_readl(host, DWMCI_RINTSTS); // Hardware asserts DWMCI_INTMSK_DTO here dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_DTO); if (mask & DWMCI_INTMSK_DTO) { // Unreachable as DTO is cleared without being handled! return 0; } Only clear interrupts that we have seen and are handling so that DTO is not missed. Signed-off-by:John Keeping <john@metanate.com> Tested-by: Jerome Forissier <jerome.forissier@linaro.org> (Rock PI 4B) Tested-by:
Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by:
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The SDMMC IOs can be in an IO domain, that has to be enabled. This is done by enabling vqmmc in the driver. This has no impact on configurations not using an IO domain, the check can then be executed on all platforms managing regulator, and the vqmmc regulator enabled on all platforms having it in their DT. Signed-off-by:
Yann Gautier <yann.gautier@foss.st.com> Reviewed-by:
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The UHS modes for SD, HS200 and HS400 modes for eMMC are not supported by the stm32_sdmmc2 driver. Make it clear by removing the corresponding caps after parsing the DT. Signed-off-by:
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To support dual data rate with STM32 sdmmc2 driver, the dedicated bit (DDR - BIT(18)) needs to be set in the CLKRC register. Clock bypass (no divider) is not allowed in this case. This is required for the eMMC DDR modes. Signed-off-by:
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Add Socionext F_SDH30_E51 IP support. The features of this IP includes CMD/DAT line delay and force card insertion mode for non-removable cards. And the IP needs to add some quirks. Signed-off-by:Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
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This patch defines a quirk to disable the block count for single block transactions. This is similar to Linux kernel commit d3fc5d71ac4d ("mmc: sdhci: add a quirk for single block transactions"). Signed-off-by: -
Get rid of discrepancy beween comment /* 250 ms */ and code which shifts by 4 thus dividing by 16. So change code to shift by 2 and make the timeout value 250 ms. Signed-off-by:
Sergei Antonov <saproj@gmail.com> Reviewed-by:
Rick Chen <rick@andestech.com> Reviewed-by:
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- Oct 21, 2022
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Tom Rini authored
- Enforce CONFIG_DM being enabled (which has been the case for all boards for a bit now) and remove non-DM_KEYBOARD options as they're also unused for some time now.
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Tom Rini authored
Rsync all defconfig files using moveconfig.py Signed-off-by:Tom Rini <trini@konsulko.com>
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Tom Rini authored
There are no platforms that have not migrated to using DM_KEYBOARD, remove the legacy option. Cc: Simon Glass <sjg@chromium.org> Signed-off-by:
Simon Glass <sjg@chromium.org>
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Tom Rini authored
There are no longer any platforms which do not enable DM, move this to a def_bool y and remove the check in the Makefile. Cc: Simon Glass <sjg@chromium.org> Signed-off-by:
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https://source.denx.de/u-boot/custodians/u-boot-at91Tom Rini authored
First set of u-boot-at91 fixes for the 2023.01 cycle: This small fixes set includes an indentation fix for sam9x60 DT and one name for one pin for sama7g5.
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Mihai Sain authored
The signal name of pin PB2 with function F is FLEXCOM11_IO1 as it is defined in the datasheet. Fixes: 558378a4 ("ARM: mach-at91: add support for new SoC sama7g5") Signed-off-by:
Mihai Sain <mihai.sain@microchip.com>
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Dario Binacchi authored
The indentation went far on the right due to an extra tab for each pinctrl sub-nodes. Signed-off-by:
Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by:
Michael Trimarchi <michael@amarulasolutions.com>
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https://source.denx.de/u-boot/custodians/u-boot-rockchipTom Rini authored
- dts update and sync for rk356x, rk3288, rk3399 from Linux; - Add rk3399 EAIDK-610 board support; - Update for puma-rk3399 board; - some fix and typo fix in different drivers;
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- Oct 20, 2022
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https://source.denx.de/u-boot/custodians/u-boot-clkTom Rini authored
Clock patches for 2023.01 This contains various fixes (some long overdue) for the next release.
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https://source.denx.de/u-boot/custodians/u-boot-sunxiTom Rini authored
Beside some rather unexciting sync of the DTs from the kernel tree, and some Kconfig cleanup, there are some improvements for the ARMv5 Allwinner family, to support boards with the F1C200s (64MB DRAM) better. We will get actual board support as soon as the DTs have passed the Linux review process. There is also support for the X96 Mate TV Box, featuring the H616 SoC and a full 4GB of DRAM. Also we found the secret to enable SPI booting on the H616 (pin PC5 must be pulled to GND), so the SPI boot support patch is now good to go. Passed the gitlab CI, plus briefly tested on Pine64-LTS, LicheePi Nano, X96 Mate and OrangePi Zero.
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Rick Chen authored
Check firmware_fdt_addr header to see if it is a valid fdt blob. Signed-off-by:
Leo Yu-Chi Liang <ycliang@andestech.com>
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Yu Chien Peter Lin authored
The IPI scheme in OpenSBI has been updated to support 8-core AE350 platform, the plicsw configuration needs to be modified accordingly. Signed-off-by:
Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by:
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Bin Meng authoredSince OpenSBI commit bf3ef53bb7f5 ("firmware: Enable FW_PIC by default"), OpenSBI runs directly at the load address without any code movement. This causes the SPL version of QEMU 'virt' U-Boot does not boot Linux kernel anymore. In that case, OpenSBI is loaded and runs at 0x81000000, and it creates a 512KiB PMP window from that address. When booting the Linux kernel, moving kernel to its linking address 0x80200000 overlaps the PMP window, and a PMP access failure is raised. Update SPL_OPENSBI_LOAD_ADDR to load OpenSBI to a safe address. Reported-by:Yangjie Zhang <pyjmstr@gmail.com> Signed-off-by:
Bin Meng <bmeng.cn@gmail.com>
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Heinrich Schuchardt authored
The k210 driver is selected by sandbox_defconfig. Building the sandbox on 32bit systems fails with: test/dm/k210_pll.c: In function ‘dm_test_k210_pll_calc_config’: include/linux/bitops.h:11:38: warning: left shift count >= width of type [-Wshift-count-overflow] 11 | #define BIT(nr) (1UL << (nr)) | ^~ test/dm/k210_pll.c:36:54: note: in expansion of macro ‘BIT’ 36 | error = abs((error - BIT(32))) >> 16; | ^~~ Use the BIT_ULL() macro to create a u64 value. Replace abs() by abs64() to get correct results on 32bit system Apply the same for the unit test. Signed-off-by:Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by:
Sean Anderson <seanga2@gmail.com>
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Heinrich Schuchardt authored
The riscv32 toolchain for GCC-12 provided by kernel.org contains libgcc.a compiled for double-float. To link to it we have to adjust how we build U-Boot. As U-Boot actually does not use floating point at all this should not make a significant difference for the produced binaries. Signed-off-by:
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Heinrich Schuchardt authored
In the sbi command use the same short texts for the legacy extensions as the SBI specification 1.0.0. Signed-off-by:
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Heinrich Schuchardt authored
If calling 'Get SBI specification version' fails, write an error message and return CMD_RET_FAILURE. Signed-off-by:
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Heinrich Schuchardt authored
The SBI command can print out the version number of the SBI implementation. Choose the correct output format for RustSBI. Signed-off-by:
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- Oct 19, 2022
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In clk_clean_rate_cache, clk->rate should update the private clock struct, in particular when CCF is activated, to save the cached rate value. When clk_get_parent_rate is called, the cached information is read from pclk->rate, with pclk = clk_get_parent(clk). As the cached is read from private clk data, the update should be done also on it. Fixes: 6b7fd312 ("clk: fix set_rate to clean up cached rates for the hierarchy") Signed-off-by:
Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by:
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Fixes: bbda2ed5 ("rockchip: clk: pll: add common pll setting funcs") Signed-off-by:
Michal Suchanek <msuchanek@suse.de> Link: https://lore.kernel.org/r/20220928104129.13240-1-msuchanek@suse.de
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All functions getting and setting clock rate use ulong for rate, only clk_get_parent_rate is an exception. Change the return value to match other clock rate funcrions. Most users directly assign the rate to unsigned long anyway, and the few users that use u64 (not s64) multiply the rate so they may need the extra bits for the result in their use case. Fixes: 4aa78300 ("dm: clk: Define clk_get_parent_rate() for clk operations") Signed-off-by:
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André Przywara authored
Some boards with the Allwinner F1C100s family SoCs use UART1 for its debug UART, so define the pins for the SPL and the pinmux name and mux value for U-Boot proper. Signed-off-by:
Andre Przywara <andre.przywara@arm.com> Reviewed-by:
Jernej Skrabec <jernej.skrabec@gmail.com>
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André Przywara authored
So far we stated the lack of a lowlevel() init function for the Allwinner F1C100s board by defining the respective SKIP_* symbol in the board's defconfig. However we don't expect any *board* to employ such low level code, so expect this to be never used for the ARMv5 Allwinner SoCs. Select the appropriate symbols in the Kconfig, so that we can remove them from the defconfig, and avoid putting them in future defconfigs for other boards. Signed-off-by:
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André Przywara authored
The default load addresses for the various payloads (kernel, DT, ramdisk) on systems with just 32MB of DRAM have some issues: For a start the preceding comment doesn't match the actual values: apparently they were copied from the 64MB S3 layout, then halved, but since 0x5 is NOT the half of 0x10, they don't match up. Also those projected maximum sizes are quite restrictive: it's not easy to build a compressed kernel image with just 4MB. The only defconfig in mainline Linux that supports the F1C100s (the only 32MB user so far) creates a 6MB compressed / 15MB uncompressed kernel. Rearrange the default load addresses to accommodate such a kernel: we allow an 7MB/16MB kernel, and up to 5MB of ramdisk, stuffing the smaller binaries like the DTB towards the end, just before the relocated U-Boot. Shrink the size for DTB and scripts on the way, there is no need for allowing up to 512K for them. Signed-off-by:
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André Przywara authored
Traditionally we assumed that every Allwinner board would come with at least 256 MB of DRAM, and set our DRAM layout accordingly. This affected both the default load addresses, but also U-Boot's own address expectations (like being loaded at 160 MB). Some SoCs come with co-packaged DRAM, but only provide 32 or 64MB. So far we special-cased those *chips*, as there was only one chip per DRAM size. However new chips force us to take a more general approach. Introduce a Kconfig symbol, which provides the minimum DRAM size of the board. If nothing else is specified, we use 256 MB, and default to smaller values for those co-packaged SoCs. Then select the different DRAM maps according to this new symbol, so that different SoCs with the same DRAM size can share those definitions. Inspired by an idea from Icenowy. This is just refactoring: compiled for all boards before and after this patch: the binaries were identical. Signed-off-by:
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As the compile error when D-Cache is enabled is gone, we can have D-Cache enabled now. Signed-off-by:
Icenowy Zheng <uwu@icenowy.me> Reviewed-by:
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The enable_caches function in architecture-specific board code is only necessary for V7A CPUs, code for both V8A and ARM926 have already declared this function. Only provide our implementation of enable_caches() for V7A CPUs. Signed-off-by:
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André Przywara authored
The X96 Mate TV box is a TV box with the Allwinner H616 SoC. It is available with up to 4GB of DRAM and 64GB eMMC. The DRAM chips require a different configuration when compared to the OrangePi Zero2, we must not use read/write training and write leveling. Add a defconfig for the box, so that we can easily build U-Boot for it. We synced the .dts file already from the kernel tree. Signed-off-by:
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prepare for rk3566 based board Signed-off-by:
FUKAUMI Naoki <naoki@radxa.com> Reviewed-by:
Kever Yang <kever.yang@rock-chips.com>
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At present the display does not work since it needs the reset driver to operate. Fix this by enabling it. Signed-off-by:
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Now that a single binary containing TPL/SPL correctly formatted for SPI flashes and U-Boot proper, can be generated by binman, let's do it. Also update the documentation to tell the user to use this newly generated file instead of manually generating and flashing the binaries. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by:
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