- Feb 08, 2022
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Seems that we need the waterlevel setting not only for PIO mode as without this at least the i.MX 8M Mini won't boot anymore when being written by such a U-Boot. Corruption has also been observed both on the i.MX 6 as well as i.MX 8M Mini when using ums on the eMMC. Fix this by setting the watermark level again regardless of whether in DMA or PIO mode. Fixes: 41c6a22f ("mmc: fsl_esdhc_imx: simplify esdhc_setup_data()") Signed-off-by:
Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by:
Fabio Estevam <festevam@gmail.com> Tested-by:
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In case the eMMC contains any GP partitions or user sets up new GP partitions, the size of these GP partitions reduce the size of the USER partition. Subtract the size of those GP partitions from the calculated size of USER partition when using `user enh start -`. The following test used to fail before: ``` u-boot=> mmc hwpartition gp1 524288 enh user enh 0 - wrrel on check Partition configuration: User Enhanced Start: 0 Bytes User Enhanced Size: 1.8 GiB User partition write reliability: on GP1 Capacity: 256 MiB ENH No GP2 partition No GP3 partition No GP4 partition Total enhanced size exceeds maximum (261 > 229) Failed! ``` The test now passes: ``` u-boot=> mmc hwpartition gp1 524288 enh user enh 0 - wrrel on check Partition configuration: User Enhanced Start: 0 Bytes User Enhanced Size: 1.5 GiB User partition write reliability: on GP1 Capacity: 256 MiB ENH No GP2 partition No GP3 partition No GP4 partition ``` Signed-off-by:Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by:
Jaehoon Chung <jh80.chung@samsung.com>
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Tom Rini authored
- J721S2 support, IPU support on DRA7, SIERRA PHY mulitlink configuration support, Nokia RX-51 DM_KEYBOARD conversion
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Signed-off-by:Pali Rohár <pali@kernel.org>
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Add configs to enable booting ethfw core in j721e Signed-off-by:Aswath Govindraju <a-govindraju@ti.com>
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Add support for QSGMII multilink configuration. Signed-off-by: -
In some cases, a single SerDes instance can be shared between two different processors, each using a separate link. In these cases, the SerDes configuration is done in an earlier boot stage. Therefore, add support to skip reconfiguring, if it is was already configured beforehand. Signed-off-by: -
Add register sequences for PCIe + QSGMII PHY multilink configuration. Signed-off-by:
Swapnil Jakhade <sjakhade@cadence.com> Signed-off-by:
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Add support for multilink configuration of Sierra PHY. Currently, maximum two links are supported. Signed-off-by:
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Add single link PCIe register configurations for no SSC and internal SSC. Also, add missing PMA lane registers for external SSC. Signed-off-by:
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PIPE phy status is used to communicate the completion of several PHY functions. Check if PHY is ready for operation while configured for PIPE mode during startup. Signed-off-by:
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Check if PMA cmn_ready is set indicating the startup process is complete. Signed-off-by:
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Add PHY PCS common register configuration sequences for single link. Update single link PCIe register sequence accordingly. Signed-off-by:
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No functional change. Rename some regmap variables as mentioned in Sierra register description documentation. Signed-off-by:
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Add support to get SSC type from DT. Signed-off-by:
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Add binding to specify Spread Spectrum Clocking mode used Signed-off-by:
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Sierra driver currently supports single link configurations only. Prepare driver to support multilink multiprotocol configurations along with different SSC modes. Signed-off-by:
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The PLL_CMNLC clocks are modelled as a child clock device of seirra. In the function device_probe, the corresponding clocks are probed before calling the device's probe. The PLL_CMNLC mux clock can only be created after the device's probe. Therefore, move assigned-clocks and assigned-clock-parents to the link nodes in U-Boot device tree file. Signed-off-by: -
Add support for probing, initializing and powering, SerDes0 instance. Signed-off-by: -
Fix the condition for setting P_ENABLE_FORCE bit, by syncing with the driver in kernel. Signed-off-by: -
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as a clock so that it's possible to select one of these two inputs from device tree. Signed-off-by: -
Add a driver of type UCLASS_PHY for each of the link nodes in the serdes instance. Signed-off-by: -
Add missing clk_disable_unprepare() in cdns_sierra_phy_remove(). Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
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Instead of having separate structure members for each input clock, add an array for the input clocks within "struct cdns_sierra_phy". This is in preparation for adding more input clocks required for supporting additional clock combination. Signed-off-by:
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No functional change. Group devm_reset_control_get() and devm_reset_control_get_optional() to a separate function. Signed-off-by:
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No functional change. Group all devm_clk_get_optional() to a separate function. Signed-off-by:
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Cadence Sierra PHY driver registers PHY using devm_phy_create() for all sub-nodes of Sierra device tree node. However Sierra device tree node can have sub-nodes for the various clocks in addtion to the PHY. Use devm_phy_create() only for nodes with name "phy" (or "link" for old device tree) which represent the actual PHY. Signed-off-by:
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Commit 39b82338 ("phy: cadence: Add driver for Sierra PHY") de-asserts PHY_RESET even before the configurations are loaded in phy_init(). However PHY_RESET should be de-asserted only after all the configurations has been initialized, instead of de-asserting in probe. Fix it here. Signed-off-by:
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Updated values of USB3 related Sierra PHY registers. This change fixes USB3 device disconnect issue observed while enternig U1/U2 state. Signed-off-by:
Sanket Parmar <sparmar@cadence.com> Signed-off-by:
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Add support for ipu early boot. Signed-off-by:
Keerthy <j-keerthy@ti.com> Signed-off-by:
Amjad Ouled-Ameur <aouledameur@baylibre.com>
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Add support for ipu early boot. Signed-off-by:
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Add ipu and the associated nodes. Signed-off-by:
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Add all the ipu early boot related nodes Signed-off-by:
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The driver enables IPU support. Basically enables the clocks, timers, watchdog timers and bare minimal MMU and supports loading the firmware from mmc. Signed-off-by:
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Add remoteproc resource handling helpers. These functions are primarily to parse the resource table and to handle different types of resources. Carveout, devmem, trace & vring resources are handled. Signed-off-by:
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Add find_next_zero_area to fetch the next zero area in the map. Signed-off-by:
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Enable fs_loader compilation at SPL Level. Signed-off-by:
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First check the presence of the ipu firmware in the boot partition. If present enable the ipu and the related clocks & then move on to load the firmware and eventually start remoteproc IPU1/IPU2. do_enable_clocks by default puts the clock domains into auto which does not work well with reset. Hence adding do_enable_ipu_clocks function. Signed-off-by:
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Add a reset driver to bring IPs out of reset. Signed-off-by:
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Expand SPL_MULTI_DTB_FIT to accommodate new SPL IPU nodes. Signed-off-by:
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