mx7ulp: Add support for Embedded Artists COM board

The Embedded Artists COM board is based on NXP i.MX7ULP.

It has a BD70528 PMIC from Rohm with discrete DCDC powering option and
improved current observability (compared to the existing NXP i.MX7ULP EVK).

Add the initial support for the board.
Signed-off-by: Fabio Estevam <festevam@gmail.com>

arch/arm/dts/Makefile

@@ -688,7 +688,8 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
 	imx7d-pico-hobbit.dtb
 
 
-dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
+dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
+	imx7ulp-evk.dtb
 
 dtb-$(CONFIG_ARCH_IMX8) += \
 	fsl-imx8qm-apalis.dtb \

arch/arm/dts/imx7ulp-com.dts

+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright 2019 NXP
+// Author: Fabio Estevam <fabio.estevam@nxp.com>
+
+/dts-v1/;
+
+#include "imx7ulp.dtsi"
+
+/ {
+	model = "Embedded Artists i.MX7ULP COM";
+	compatible = "ea,imx7ulp-com", "fsl,imx7ulp";
+
+	chosen {
+		stdout-path = &lpuart4;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x60000000 0x8000000>;
+	};
+};
+
+&lpuart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart4>;
+	status = "okay";
+};
+
+&usbotg1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usbotg1_id>;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&usbphy1 {
+	fsl,tx-d-cal = <88>;
+};
+
+&usdhc0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc0>;
+	non-removable;
+	bus-width = <8>;
+	no-1-8-v;
+	status = "okay";
+};
+
+&iomuxc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1>;
+
+	pinctrl_hog_1: hoggrp-1 {
+		fsl,pins = <
+			IMX7ULP_PAD_PTC1__PTC1		0x20000
+		>;
+	};
+
+	pinctrl_lpuart4: lpuart4grp {
+		fsl,pins = <
+			IMX7ULP_PAD_PTC3__LPUART4_RX	0x3
+			IMX7ULP_PAD_PTC2__LPUART4_TX	0x3
+		>;
+	};
+
+	pinctrl_usdhc0: usdhc0grp {
+		fsl,pins = <
+			IMX7ULP_PAD_PTD1__SDHC0_CMD	0x43
+			IMX7ULP_PAD_PTD2__SDHC0_CLK	0x10042
+			IMX7ULP_PAD_PTD3__SDHC0_D7	0x43
+			IMX7ULP_PAD_PTD4__SDHC0_D6	0x43
+			IMX7ULP_PAD_PTD5__SDHC0_D5	0x43
+			IMX7ULP_PAD_PTD6__SDHC0_D4	0x43
+			IMX7ULP_PAD_PTD7__SDHC0_D3	0x43
+			IMX7ULP_PAD_PTD8__SDHC0_D2	0x43
+			IMX7ULP_PAD_PTD9__SDHC0_D1	0x43
+			IMX7ULP_PAD_PTD10__SDHC0_D0	0x43
+			IMX7ULP_PAD_PTD11__SDHC0_DQS	0x42
+		>;
+	};
+
+	pinctrl_usbotg1_id: otg1idgrp {
+		fsl,pins = <
+			IMX7ULP_PAD_PTC13__USB0_ID	0x10003
+		>;
+	};
+};

arch/arm/mach-imx/mx7ulp/Kconfig

@@ -15,6 +15,11 @@ choice
 	prompt "MX7ULP board select"
 	optional
 
+config TARGET_MX7ULP_COM
+	bool "Support MX7ULP COM board"
+	select MX7ULP
+	select SYS_ARCH_TIMER
+
 config TARGET_MX7ULP_EVK
 	bool "Support mx7ulp EVK board"
 	select MX7ULP
@@ -22,6 +27,7 @@ config TARGET_MX7ULP_EVK
 
 endchoice
 
+source "board/ea/mx7ulp_com/Kconfig"
 source "board/freescale/mx7ulp_evk/Kconfig"
 
 endif

board/ea/mx7ulp_com/Kconfig

+if TARGET_MX7ULP_COM
+
+config SYS_BOARD
+	default "mx7ulp_com"
+
+config SYS_VENDOR
+	default "ea"
+
+config SYS_CONFIG_NAME
+	default "mx7ulp_com"
+
+endif

board/ea/mx7ulp_com/MAINTAINERS

+MX7ULPCOM BOARD
+M:	Fabio Estevam <festevam@gmail.com>
+S:	Maintained
+F:	board/ea/mx7ulp_com/
+F:	include/configs/mx7ulp_com.h
+F:	configs/mx7ulp_com_defconfig

board/ea/mx7ulp_com/Makefile

+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx7ulp_com.o

board/ea/mx7ulp_com/imximage.cfg

+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx7ulp_evk/plugin.bin 0x2F020000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4   0x403f00dc 0x00000000
+DATA 4   0x403e0040 0x01000020
+DATA 4   0x403e0500 0x01000000
+DATA 4   0x403e050c 0x80808080
+DATA 4   0x403e0508 0x00160002
+DATA 4   0x403E0510 0x00000001
+DATA 4   0x403E0514 0x00000014
+DATA 4   0x403e0500 0x00000001
+CHECK_BITS_SET 4 0x403e0500 0x01000000
+/*
+ * Default PFD0 divide is 27, which generates:
+ * PFD0 Freq = A7 APLL (528MHz) * 18 / 27 = 352MHz
+ *
+ * i.MX7ULP COM board can not run DDR at 352MHz, so
+ * use a divider of 30 (0x1E), which gives:
+ *
+ * PFD0 Freq = A7 APLL (528MHz) * 18 / 30 = 316.8MHz
+ */
+DATA 4   0x403e050c 0x8080801E
+CHECK_BITS_SET 4 0x403e050c 0x00000040
+DATA 4   0x403E0030 0x00000001
+DATA 4   0x403e0040 0x11000020
+DATA 4   0x403f00dc 0x42000000
+
+DATA 4   0x40B300AC 0x40000000
+
+DATA 4   0x40AD0128 0x00040000
+DATA 4   0x40AD00F8 0x00000000
+DATA 4   0x40AD00D8 0x00000180
+DATA 4   0x40AD0104 0x00000180
+DATA 4   0x40AD0108 0x00000180
+DATA 4   0x40AD0124 0x00010000
+DATA 4   0x40AD0080 0x0000018C
+DATA 4   0x40AD0084 0x0000018C
+DATA 4   0x40AD0088 0x0000018C
+DATA 4   0x40AD008C 0x0000018C
+
+DATA 4   0x40AD0120 0x00010000
+DATA 4   0x40AD010C 0x00000180
+DATA 4   0x40AD0110 0x00000180
+DATA 4   0x40AD0114 0x00000180
+DATA 4   0x40AD0118 0x00000180
+DATA 4   0x40AD0090 0x00000180
+DATA 4   0x40AD0094 0x00000180
+DATA 4   0x40AD0098 0x00000180
+DATA 4   0x40AD009C 0x00000180
+
+DATA 4   0x40AD00E0 0x00040000
+DATA 4   0x40AD00E4 0x00040000
+
+DATA 4   0x40AB001C 0x00008000
+DATA 4   0x40AB085C 0x0D3900A0
+DATA 4   0x40AB0800 0xA1390003
+DATA 4   0x40AB0890 0x00400000
+DATA 4   0x40AB081C 0x33333333
+DATA 4   0x40AB0820 0x33333333
+DATA 4   0x40AB0824 0x33333333
+DATA 4   0x40AB0828 0x33333333
+DATA 4   0x40AB08C0 0x24922492
+DATA 4   0x40AB0848 0x3A3E3838
+DATA 4   0x40AB0850 0x28282C2A
+DATA 4   0x40AB083C 0x20000000
+DATA 4   0x40AB0840 0x00000000
+DATA 4   0x40AB08B8 0x00000800
+DATA 4   0x40AB000C 0x292C40F5
+DATA 4   0x40AB0004 0x00020064
+DATA 4   0x40AB0010 0xB6AD0A83
+DATA 4   0x40AB0014 0x00C70093
+DATA 4   0x40AB0018 0x00211708
+DATA 4   0x40AB002C 0x0F9F26D2
+DATA 4   0x40AB0030 0x009F0E10
+DATA 4   0x40AB0038 0x00130556
+DATA 4   0x40AB0008 0x12272000
+DATA 4   0x40AB0040 0x0000003F
+DATA 4   0x40AB0000 0xC3110000
+DATA 4   0x40AB001C 0x00008010
+DATA 4   0x40AB001C 0x00008018
+DATA 4   0x40AB001C 0x003F8030
+DATA 4   0x40AB001C 0xFF0A8030
+DATA 4   0x40AB001C 0x82018030
+DATA 4   0x40AB001C 0x06028030
+DATA 4   0x40AB001C 0x01038030
+DATA 4   0x40AB001C 0x003F8038
+DATA 4   0x40AB001C 0xFF0A8038
+DATA 4   0x40AB001C 0x82018038
+DATA 4   0x40AB001C 0x06028038
+DATA 4   0x40AB001C 0x01038038
+DATA 4   0x40AB083C 0xA0000000
+DATA 4   0x40AB083C 0xA0000000
+DATA 4   0x40AB0020 0x00001800
+DATA 4   0x40AB0800 0xA1310003
+DATA 4   0x40AB001C 0x00000000
+#endif

board/ea/mx7ulp_com/mx7ulp_com.c

+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mx7ulp-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/gpio.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL		(PAD_CTL_PUS_UP)
+
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+
+	return 0;
+}
+
+static iomux_cfg_t const lpuart4_pads[] = {
+	MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+	mx7ulp_iomux_setup_multiple_pads(lpuart4_pads,
+					 ARRAY_SIZE(lpuart4_pads));
+}
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	return 0;
+}

configs/mx7ulp_com_defconfig

+CONFIG_ARM=y
+CONFIG_ARCH_MX7ULP=y
+CONFIG_SYS_TEXT_BASE=0x67800000
+CONFIG_LDO_ENABLED_MODE=y
+CONFIG_TARGET_MX7ULP_COM=y
+CONFIG_ENV_SIZE=0x2000
+CONFIG_ENV_OFFSET=0xC0000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/ea/mx7ulp_com/imximage.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx7ulp-com"
+CONFIG_BOUNCE_BUFFER=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_READ=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-com"
+CONFIG_ENV_IS_IN_MMC=y
+# CONFIG_NET is not set
+CONFIG_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_IMX_RGPIO2P=y
+# CONFIG_MXC_GPIO is not set
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_DM_MMC=y
+CONFIG_FSL_USDHC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0
+CONFIG_SF_DEFAULT_SPEED=40000000
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7ULP=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_FSL_QSPI=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="FSL"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0525
+CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
+CONFIG_CI_UDC=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_ULP_WATCHDOG=y

include/configs/mx7ulp_com.h

+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Embedded Artists i.MX7ULP COM board.
+ */
+
+#ifndef __MX7ULP_COM_CONFIG_H
+#define __MX7ULP_COM_CONFIG_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_BOARD_POSTCLK_INIT
+#define CONFIG_SYS_BOOTM_LEN		0x1000000
+
+#define SRC_BASE_ADDR			CMC1_RBASE
+#define IRAM_BASE_ADDR			OCRAM_0_BASE
+#define IOMUXC_BASE_ADDR		IOMUXC1_RBASE
+
+/*
+ * Detect overlap between U-Boot image and environment area in build-time
+ *
+ * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot-dtb.imx offset
+ * CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408
+ *
+ * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so
+ * write the direct value here
+ */
+#define CONFIG_BOARD_SIZE_LIMIT		785408
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_MMCROOT			"/dev/mmcblk0p2"
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+/* Using ULP WDOG for reset */
+#define WDOG_BASE_ADDR			WDG1_RBASE
+
+#define CONFIG_SYS_HZ_CLOCK		1000000 /* Fixed at 1MHz from TSTMR */
+
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(8 * SZ_1M)
+
+/* UART */
+#define LPUART_BASE			LPUART4_RBASE
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* Physical Memory Map */
+
+#define PHYS_SDRAM			0x60000000
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+
+#define CONFIG_LOADADDR			0x60800000
+
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + SZ_512M)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"image=zImage\0" \
+	"console=ttyLP0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=imx7ulp-com.dtb\0" \
+	"fdt_addr=0x63000000\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if run loadfdt; then " \
+			"bootz ${loadaddr} - ${fdt_addr}; " \
+		"fi;\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if run loadimage; then " \
+		"run mmcboot; " \
+	"fi; " \
+
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	SZ_256K
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+#define CONFIG_CMD_CACHE
+#endif
+
+#define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
+#endif	/* __CONFIG_H */