Commit d8a3f525 authored by Tom Rini's avatar Tom Rini
Browse files

Merge tag 'u-boot-imx-20200107' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

New for 2020.04
---------------

- New boards
	Embedded Artists COM board
	Xea Board
- Switch to DM:
	Aristainetos boards
	Toradex colibri (DM_ETH)
	iCubox
	GE bx50v3
	mx7dsabre (DM_ETH)
	cx9020
- New features:
	Bootaux with elf files
	Default SYS_THUMB_BUILD for i.MX6/7
- Fixes:
	DHCOM i.MX6 PDK
	Engicam
	i.MX8M tools (imx8m_image)

Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/633679664
parents ac0f978a b6e7ef4b
......@@ -823,6 +823,7 @@ config ARCH_MX7ULP
select CPU_V7A
select ROM_UNIFIED_SECTIONS
imply MXC_GPIO
imply SYS_THUMB_BUILD
config ARCH_MX7
bool "Freescale MX7"
......@@ -833,6 +834,7 @@ config ARCH_MX7
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
imply MXC_GPIO
imply SYS_THUMB_BUILD
config ARCH_MX6
bool "Freescale MX6"
......@@ -840,8 +842,8 @@ config ARCH_MX6
select SYS_FSL_HAS_SEC if IMX_HAB
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
select SYS_THUMB_BUILD if SPL
imply MXC_GPIO
imply SYS_THUMB_BUILD
if ARCH_MX6
config SPL_LDSCRIPT
......
......@@ -98,13 +98,16 @@ int arch_cpu_init(void)
/*
* Enable NAND clock
*/
/* Clear bypass bit */
/* Set bypass bit */
writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
&clkctrl_regs->hw_clkctrl_clkseq_set);
/* Set GPMI clock to ref_gpmi / 12 */
/* Set GPMI clock to ref_xtal / 1 */
clrbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, CLKCTRL_GPMI_CLKGATE);
while (readl(&clkctrl_regs->hw_clkctrl_gpmi) & CLKCTRL_GPMI_CLKGATE)
;
clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);
CLKCTRL_GPMI_DIV_MASK, 1);
udelay(1000);
......
......@@ -25,9 +25,7 @@ static bd_t bdata __section(".data");
/*
* This delay function is intended to be used only in early stage of boot, where
* clock are not set up yet. The timer used here is reset on every boot and
* takes a few seconds to roll. The boot doesn't take that long, so to keep the
* code simple, it doesn't take rolling into consideration.
* clock are not set up yet.
*/
void early_delay(int delay)
{
......@@ -35,8 +33,7 @@ void early_delay(int delay)
(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
uint32_t st = readl(&digctl_regs->hw_digctl_microseconds);
st += delay;
while (st > readl(&digctl_regs->hw_digctl_microseconds))
while (readl(&digctl_regs->hw_digctl_microseconds) - st <= delay)
;
}
......
......@@ -570,14 +570,34 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
vf610-pcm052.dtb \
vf610-bk4r1.dtb
dtb-$(CONFIG_MX28) += \
imx28-xea.dtb
dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \
imx53-kp.dtb \
imx53-m53menlo.dtb
ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),)
dtb-y += \
imx6dl-aristainetos2_4.dtb \
imx6dl-aristainetos2_7.dtb \
imx6dl-aristainetos2b_4.dtb \
imx6dl-aristainetos2b_7.dtb \
imx6dl-aristainetos2b_csl_4.dtb \
imx6dl-aristainetos2b_csl_7.dtb \
imx6dl-aristainetos2c_4.dtb \
imx6dl-aristainetos2c_7.dtb \
imx6dl-brppt2.dtb \
imx6dl-cubox-i.dtb \
imx6dl-cubox-i-emmc-som-v15.dtb \
imx6dl-cubox-i-som-v15.dtb \
imx6dl-dhcom-pdk2.dtb \
imx6dl-hummingboard2.dtb \
imx6dl-hummingboard2-emmc-som-v15.dtb \
imx6dl-hummingboard2-som-v15.dtb \
imx6dl-hummingboard.dtb \
imx6dl-hummingboard-emmc-som-v15.dtb \
imx6dl-hummingboard-som-v15.dtb \
imx6dl-icore.dtb \
imx6dl-icore-mipi.dtb \
imx6dl-icore-rqs.dtb \
......@@ -594,8 +614,17 @@ ifneq ($(CONFIG_MX6Q)$(CONFIG_MX6QDL),)
dtb-y += \
imx6-apalis.dtb \
imx6q-cm-fx6.dtb \
imx6q-cubox-i.dtb \
imx6q-cubox-i-emmc-som-v15.dtb \
imx6q-cubox-i-som-v15.dtb \
imx6q-dhcom-pdk2.dtb \
imx6q-display5.dtb \
imx6q-hummingboard2.dtb \
imx6q-hummingboard2-emmc-som-v15.dtb \
imx6q-hummingboard2-som-v15.dtb \
imx6q-hummingboard.dtb \
imx6q-hummingboard-emmc-som-v15.dtb \
imx6q-hummingboard-som-v15.dtb \
imx6q-icore.dtb \
imx6q-icore-mipi.dtb \
imx6q-icore-rqs.dtb \
......@@ -634,14 +663,14 @@ dtb-$(CONFIG_MX6UL) += \
imx6ul-9x9-evk.dtb \
imx6ul-9x9-evk.dtb \
imx6ul-liteboard.dtb \
imx6ul-phycore-segin.dtb \
imx6ul-phytec-segin-ff-rdk-nand.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-pico-pi.dtb
dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri.dtb \
imx6ull-phycore-segin.dtb \
imx6ull-phytec-segin-ff-rdk-emmc.dtb \
imx6ull-dart-6ul.dtb \
imx6ulz-14x14-evk.dtb
......@@ -659,7 +688,8 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
imx7d-pico-hobbit.dtb
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
imx7ulp-evk.dtb
dtb-$(CONFIG_ARCH_IMX8) += \
fsl-imx8qm-apalis.dtb \
......@@ -840,7 +870,12 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt8516-pumpkin.dtb \
mt8518-ap1-emmc.dtb
dtb-$(CONFIG_TARGET_GE_BX50V3) += imx6q-bx50v3.dtb
dtb-$(CONFIG_TARGET_GE_BX50V3) += \
imx6q-bx50v3.dtb \
imx6q-b850v3.dtb \
imx6q-b650v3.dtb \
imx6q-b450v3.dtb
dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
dtb-$(CONFIG_TARGET_VEXPRESS_CA5X2) += vexpress-v2p-ca5s.dtb
......
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
*
* SPDX-License-Identifier: GPL-2.0+ or X11
*/
/*
* The minimal augmentation DTS U-Boot file to allow eMMC driver
* configuration in SPL for falcon boot.
*/
#include "imx28-u-boot.dtsi"
/ {
apb@80000000 {
u-boot,dm-spl;
apbh@80000000 {
u-boot,dm-spl;
};
apbx@80040000 {
u-boot,dm-spl;
};
};
};
&clks {
u-boot,dm-spl;
};
&gpio0 {
u-boot,dm-spl;
};
&pinctrl {
u-boot,dm-spl;
};
&ssp0 {
u-boot,dm-spl;
};
&ssp3 {
u-boot,dm-spl;
};
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019
* Lukasz Majewski, DENX Software Engineering, lukma@denx.de
*
* SPDX-License-Identifier: GPL-2.0+ or X11
*
*/
/dts-v1/;
#include "imx28.dtsi"
/ {
model = "Liebherr (LWE) XEA i.MX28 Board";
compatible = "lwe,xea", "fsl,imx28";
aliases {
spi3 = &ssp3;
};
memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x10000000>;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_fec_3v3: regulator-fec-3v3 {
compatible = "regulator-fixed";
regulator-name = "fec-3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
};
};
&mac0 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a>;
phy-supply = <&reg_fec_3v3>;
phy-reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
phy-reset-post-delay = <1>;
status = "okay";
fixed-link {
speed = <100>;
full-duplex;
};
};
&ssp0 {
compatible = "fsl,imx28-mmc";
pinctrl-names = "default";
pinctrl-0 = <&mmc0_8bit_pins_a>;
bus-width = <8>;
vmmc-supply = <&reg_3p3v>;
non-removable;
status = "okay";
};
&ssp3 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx28-spi";
pinctrl-names = "default";
pinctrl-0 = <&spi3_pins_b>;
status = "okay";
spi-max-frequency = <40000000>;
num-cs = <2>;
flash0: s25fl256s@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <40000000>;
reg = <0>;
partition@0 {
label = "SPL (spi)";
reg = <0x0 0x10000>;
read-only;
};
partition@1 {
label = "u-boot (spi)";
reg = <0x10000 0x70000>;
read-only;
};
partition@2 {
label = "uboot-env (spi)";
reg = <0x80000 0x20000>;
};
partition@3 {
label = "kernel (spi)";
reg = <0x100000 0x400000>;
};
partition@4 {
label = "swupdate (spi)";
reg = <0x50000 0x800000>;
};
};
};
......@@ -36,7 +36,6 @@
MX53_PAD_GPIO_1__GPIO1_1 0x80000000
MX53_PAD_GPIO_4__GPIO1_4 0x80000000
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000
MX53_PAD_GPIO_16__GPIO7_11 0x80000000
MX53_PAD_EIM_OE__EMI_WEIM_OE 0x80000000
......@@ -99,17 +98,6 @@
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
MX53_PAD_FEC_MDC__FEC_MDC 0x4
MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
......@@ -148,6 +136,21 @@
>;
};
pinctrl_fec0: fec0grp {
fsl,pins = <
MX53_PAD_FEC_MDC__FEC_MDC 0x4
MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
......@@ -209,5 +212,20 @@
pinctrl-names = "default";
phy-mode = "rmii";
phy-reset-gpios = <&gpio7 6 0>;
pinctrl-0 = <&pinctrl_fec0>;
status = "okay";
fixed-link { /* RMII fixed link to KZ8863 */
speed = <100>;
full-duplex;
};
};
&usbh1 {
phy_type = "utmi";
status = "okay";
};
&usbotg {
dr_mode = "host";
status = "okay";
};
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Copyright 2019 Collabora Ltd
* Copyright 2019 General Electric Company
*/
/ {
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
};
};
This diff is collapsed.
......@@ -22,6 +22,7 @@
mmc1 = &usdhc1;
mmc2 = &usdhc2;
usb0 = &usbotg; /* required for ums */
ethernet0 = &fec;
};
chosen {
......@@ -197,6 +198,27 @@
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii";
phy-handle = <&ethphy>;
phy-reset-duration = <10>;
phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@7 {
interrupt-parent = <&gpio1>;
interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
reg = <7>;
};
};
};
/* Apalis Serial ATA */
&sata {
status = "okay";
......
......@@ -21,6 +21,7 @@
mmc0 = &usdhc3;
mmc1 = &usdhc1;
usb0 = &usbotg; /* required for ums */
ethernet0 = &fec;
};
chosen {
......@@ -46,6 +47,25 @@
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
phy-handle = <&ethphy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@0 {
reg = <0>;
micrel,led-mode = <0>;
status = "okay";
};
};
};
/*
* PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
* touch screen controller
......
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
*/
#include <imx6qdl-aristainetos2-u-boot.dtsi>
&lcd_panel {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp>;
enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
backlight = <&backlight>;
};
// SPDX-License-Identifier: (GPL-2.0)
/*
* support for the imx6 based aristainetos2 board
* parts for 4.3 inch LG display on spi1 port0
*
* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
* Copyright (C) 2015 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
#include "imx6dl-aristainetos2_4.dtsi"
#include "imx6qdl-aristainetos2.dtsi"
/ {
model = "aristainetos2 i.MX6 Dual Lite Board 4";
compatible = "fsl,imx6dl";
};
&ecspi1 {
lcd_panel: display@0 {
compatible = "lg,lg4573";
spi-max-frequency = <10000000>;
reg = <0>;
power-on-delay = <10>;
display-timings {
480x800p57 {
native-mode;
clock-frequency = <27000027>;
hactive = <480>;
vactive = <800>;
hfront-porch = <10>;
hback-porch = <59>;
hsync-len = <10>;
vback-porch = <15>;
vfront-porch = <15>;
vsync-len = <15>;
hsync-active = <1>;
vsync-active = <1>;
};
};
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};
};
// SPDX-License-Identifier: (GPL-2.0)
/*
* support for the imx6 based aristainetos2 board
* parts for 4.3 inch LG display on the parallel port and atmel maxtouch
*
* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
* Copyright (C) 2015 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
#include "imx6dl.dtsi"
/ {
display0: disp0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx-parallel-display";
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp>;
port@0 {
reg = <0>;
display0_in: endpoint {
remote-endpoint = <&ipu1_di0_disp0>;
};
};
port@1 {
reg = <1>;
display_out: endpoint {
remote-endpoint = <&panel_in>;
};
};
};
};
&i2c3 {
touch: touch@4b {
compatible = "atmel,maxtouch";
reg = <0x4b>;
interrupt-parent = <&gpio2>;
interrupts = <9 8>;
};
};
&ipu1_di0_disp0 {
remote-endpoint = <&display0_in>;
};
&iomuxc {
pinctrl_ipu_disp: ipudisp1grp {
fsl,pins = <
MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x31
MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xE1
MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xE1
MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xE1
MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xE1
MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xE1
MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xE1
MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xE1
MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xE1
MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xE1
MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xE1
MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xE1
MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xE1
MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xE1
MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xE1
MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xE1
MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xe1
MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xE1
MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xE1
MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xE1
MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xE1
MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xE1
MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xE1
MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xE1
MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xE1
MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xE1
>;
};
};
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
*/
#include <imx6qdl-aristainetos2-u-boot.dtsi>
/ {