rcar: i2c: Migrate SYS_I2C_SH to Kconfig

- Migrate SYS_I2C_SH and related defines to Kconfig
- Remove currently unused SYS_I2C_SH related defines
- Cleanup related README section.

Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>

README

@@ -1484,26 +1484,6 @@ The following options need to be configured:
 		  - CONFIG_SYS_I2C_PPC4XX_CH0 activate hardware channel 0
 		  - CONFIG_SYS_I2C_PPC4XX_CH1 activate hardware channel 1
 
-		- drivers/i2c/rcar_i2c.c:
-		  - activate this driver with CONFIG_SYS_I2C_RCAR
-		  - This driver adds 4 i2c buses
-
-		- drivers/i2c/sh_i2c.c:
-		  - activate this driver with CONFIG_SYS_I2C_SH
-		  - This driver adds from 2 to 5 i2c buses
-
-		  - CONFIG_SYS_I2C_SH_BASE0 for setting the register channel 0
-		  - CONFIG_SYS_I2C_SH_SPEED0 for for the speed channel 0
-		  - CONFIG_SYS_I2C_SH_BASE1 for setting the register channel 1
-		  - CONFIG_SYS_I2C_SH_SPEED1 for for the speed channel 1
-		  - CONFIG_SYS_I2C_SH_BASE2 for setting the register channel 2
-		  - CONFIG_SYS_I2C_SH_SPEED2 for for the speed channel 2
-		  - CONFIG_SYS_I2C_SH_BASE3 for setting the register channel 3
-		  - CONFIG_SYS_I2C_SH_SPEED3 for for the speed channel 3
-		  - CONFIG_SYS_I2C_SH_BASE4 for setting the register channel 4
-		  - CONFIG_SYS_I2C_SH_SPEED4 for for the speed channel 4
-		  - CONFIG_SYS_I2C_SH_NUM_CONTROLLERS for number of i2c buses
-
 		- drivers/i2c/s3c24x0_i2c.c:
 		  - activate this driver with CONFIG_SYS_I2C_S3C24X0
 		  - This driver adds i2c buses (11 for Exynos5250, Exynos5420

arch/arm/mach-rmobile/include/mach/r8a7790.h

@@ -10,10 +10,6 @@
 
 #include "rcar-base.h"
 
-/* SH-I2C */
-#define CONFIG_SYS_I2C_SH_BASE2	0xE6520000
-#define CONFIG_SYS_I2C_SH_BASE3	0xE60B0000
-
 /* Module stop control/status register bits */
 #define MSTP0_BITS	0x00640801
 #define MSTP1_BITS	0xDB6E9BDF

arch/arm/mach-rmobile/include/mach/r8a7791.h

@@ -13,9 +13,6 @@
  * R-Car (R8A7791) I/O Addresses
  */
 
-/* SH-I2C */
-#define CONFIG_SYS_I2C_SH_BASE2	0xE60B0000
-
 /* SDHI */
 #define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
 #define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000

arch/arm/mach-rmobile/include/mach/r8a7792.h

@@ -10,10 +10,6 @@
 
 #include "rcar-base.h"
 
-/* SH-I2C */
-#define CONFIG_SYS_I2C_SH_BASE2	0xE6520000
-#define CONFIG_SYS_I2C_SH_BASE3	0xE60B0000
-
 /* Module stop control/status register bits */
 #define MSTP0_BITS	0x00400801
 #define MSTP1_BITS	0x9B6F987F

arch/arm/mach-rmobile/include/mach/r8a7793.h

@@ -14,9 +14,6 @@
  * R8A7793 I/O Addresses
  */
 
-/* SH-I2C */
-#define CONFIG_SYS_I2C_SH_BASE2	0xE60B0000
-
 /* SDHI */
 #define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
 #define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000

arch/arm/mach-rmobile/include/mach/r8a7794.h

@@ -10,9 +10,6 @@
 
 #include "rcar-base.h"
 
-/* SH-I2C */
-#define CONFIG_SYS_I2C_SH_BASE2	0xE60B0000
-
 /* Module stop control/status register bits */
 #define MSTP0_BITS	0x00440801
 #define MSTP1_BITS	0x936899DA

arch/arm/mach-rmobile/include/mach/rcar-base.h

@@ -70,14 +70,6 @@
 #define SMSTPCR10		0xE6150998
 #define SMSTPCR11		0xE615099C
 
-/*
- * SH-I2C
- * Ch2 and ch3 are different address. These are defined
- * in the header of each SoCs.
- */
-#define CONFIG_SYS_I2C_SH_BASE0	0xE6500000
-#define CONFIG_SYS_I2C_SH_BASE1	0xE6510000
-
 /* RCAR-I2C */
 #define CONFIG_SYS_RCAR_I2C0_BASE	0xE6508000
 #define CONFIG_SYS_RCAR_I2C1_BASE	0xE6518000

arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h

@@ -74,9 +74,6 @@
 #define PUEN_USB1_OVC   (1 << 2)
 #define PUEN_USB1_PWEN  (1 << 1)
 
-/* IICDVFS (I2C) */
-#define CONFIG_SYS_I2C_SH_BASE0	0xE60B0000
-
 #ifndef __ASSEMBLY__
 #include <asm/types.h>
 #include <linux/bitops.h>

configs/kzm9g_defconfig

@@ -25,6 +25,7 @@ CONFIG_ENV_IS_IN_FLASH=y
 CONFIG_ENV_ADDR=0x40000
 CONFIG_VERSION_VARIABLE=y
 CONFIG_SYS_I2C_LEGACY=y
+CONFIG_SYS_I2C_SH=y
 # CONFIG_MMC is not set
 CONFIG_MTD=y
 CONFIG_MTD_NOR_FLASH=y

drivers/i2c/Kconfig

@@ -449,6 +449,54 @@ config SYS_I2C_SANDBOX
 	  bus. Devices can be attached to the bus using the device tree
 	  which specifies the driver to use.  See sandbox.dts as an example.
 
+config SYS_I2C_SH
+	bool "Legacy SuperH I2C interface"
+	depends on ARCH_RMOBILE && SYS_I2C_LEGACY
+	help
+	  Enable the legacy SuperH I2C interface.
+
+if SYS_I2C_SH
+config SYS_I2C_SH_NUM_CONTROLLERS
+	int
+	default 5
+
+config SYS_I2C_SH_BASE0
+	hex
+	default 0xE6820000
+
+config SYS_I2C_SH_BASE1
+	hex
+	default 0xE6822000
+
+config SYS_I2C_SH_BASE2
+	hex
+	default 0xE6824000
+
+config SYS_I2C_SH_BASE3
+	hex
+	default 0xE6826000
+
+config SYS_I2C_SH_BASE4
+	hex
+	default 0xE6828000
+
+config SH_I2C_8BIT
+	bool
+	default y
+
+config SH_I2C_DATA_HIGH
+	int
+	default 4
+
+config SH_I2C_DATA_LOW
+	int
+	default 5
+
+config SH_I2C_CLOCK
+	int
+	default 104000000
+endif
+
 config SYS_I2C_SOFT
 	bool "Legacy software I2C interface"
 	help

drivers/i2c/sh_i2c.c

@@ -294,20 +294,20 @@ static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap,
  * Register RCAR i2c adapters
  */
 U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
-	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0)
+	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 0)
 #ifdef CONFIG_SYS_I2C_SH_BASE1
 U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
-	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1)
+	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 1)
 #endif
 #ifdef CONFIG_SYS_I2C_SH_BASE2
 U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
-	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2)
+	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 2)
 #endif
 #ifdef CONFIG_SYS_I2C_SH_BASE3
 U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
-	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3)
+	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 3)
 #endif
 #ifdef CONFIG_SYS_I2C_SH_BASE4
 U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
-	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4)
+	sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SPEED, 0, 4)
 #endif

include/configs/kzm9g.h

@@ -82,22 +82,4 @@
 
 #define CONFIG_NFS_TIMEOUT 10000UL
 
-/* I2C */
-#define CONFIG_SYS_I2C_SH
-#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5
-#define CONFIG_SYS_I2C_SH_BASE0	0xE6820000
-#define CONFIG_SYS_I2C_SH_SPEED0	100000
-#define CONFIG_SYS_I2C_SH_BASE1	0xE6822000
-#define CONFIG_SYS_I2C_SH_SPEED1	100000
-#define CONFIG_SYS_I2C_SH_BASE2	0xE6824000
-#define CONFIG_SYS_I2C_SH_SPEED2	100000
-#define CONFIG_SYS_I2C_SH_BASE3	0xE6826000
-#define CONFIG_SYS_I2C_SH_SPEED3	100000
-#define CONFIG_SYS_I2C_SH_BASE4	0xE6828000
-#define CONFIG_SYS_I2C_SH_SPEED4	100000
-#define CONFIG_SH_I2C_8BIT
-#define CONFIG_SH_I2C_DATA_HIGH 4
-#define CONFIG_SH_I2C_DATA_LOW  5
-#define CONFIG_SH_I2C_CLOCK     104000000 /* 104 MHz */
-
 #endif /* __KZM9G_H */