Commit 7f900eab authored by Michael Walle's avatar Michael Walle Committed by Priyanka Jain
Browse files

arm: dts: ls1028a: sync the fsl-ls1028a.dtsi with linux



Now that everything is prepared, copy the fsl-ls1028a.dtsi from the
linux kernel v5.14.12.

Notable changes:
 - second watchdog added
 - the number of chip selects of the SPI controller is now correct and
   reflects what the hardware offers
 - the LPUARTs have the correct clock parent
 - USB controllers are enabled by default, which was already the case
   before this sync because all board enabled all the USB controller
   nodes. A linux patch to fix this is pending.
 - the eSDHC controller changes from big-endian to little-endian, but
   that property seems to be not used at all.
Signed-off-by: default avatarMichael Walle <michael@walle.cc>
Reviewed-by: default avatarVladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain's avatarPriyanka Jain <priyanka.jain@nxp.com>
parent d08011d7
// SPDX-License-Identifier: GPL-2.0+ OR X11
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* NXP ls1028a SOC common device tree source
* Device Tree Include file for NXP Layerscape-1028A family SoC.
*
* Copyright 2019-2020 NXP
* Copyright 2018-2020 NXP
*
* Harninder Rai <harninder.rai@nxp.com>
*
*/
#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "fsl,ls1028a";
......@@ -14,6 +18,54 @@
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0>;
enable-method = "psci";
clocks = <&clockgen QORIQ_CLK_CMUX 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PW20>;
#cooling-cells = <2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x1>;
enable-method = "psci";
clocks = <&clockgen QORIQ_CLK_CMUX 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PW20>;
#cooling-cells = <2>;
};
l2: l2-cache {
compatible = "cache";
};
};
idle-states {
/*
* PSCI node is not added default, U-boot will add missing
* parts if it determines to use PSCI.
*/
entry-method = "psci";
CPU_PW20: cpu-pw20 {
compatible = "arm,idle-state";
idle-state-name = "PW20";
arm,psci-suspend-param = <0x0>;
entry-latency-us = <2000>;
exit-latency-us = <2000>;
min-residency-us = <6000>;
};
};
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
......@@ -21,14 +73,33 @@
clock-output-names = "sysclk";
};
gic: interrupt-controller@6000000 {
compatible = "arm,gic-v3";
reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
<0x0 0x06040000 0 0x40000>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
IRQ_TYPE_LEVEL_LOW)>;
osc_27m: clock-osc-27m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <27000000>;
clock-output-names = "phy_27m";
};
dpclk: clock-controller@f1f0000 {
compatible = "fsl,ls1028a-plldig";
reg = <0x0 0xf1f0000 0x0 0xffff>;
#clock-cells = <0>;
clocks = <&osc_27m>;
};
firmware {
optee: optee {
compatible = "linaro,optee-tz";
method = "smc";
status = "disabled";
};
};
reboot {
compatible ="syscon-reboot";
regmap = <&rst>;
offset = <0>;
mask = <0x02>;
};
timer {
......@@ -43,13 +114,123 @@
IRQ_TYPE_LEVEL_LOW)>;
};
pmu {
compatible = "arm,cortex-a72-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@6000000 {
compatible= "arm,gic-v3";
#address-cells = <2>;
#size-cells = <2>;
ranges;
reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */
<0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
#interrupt-cells= <3>;
interrupt-controller;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
IRQ_TYPE_LEVEL_LOW)>;
its: gic-its@6020000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */
};
};
thermal-zones {
ddr-controller {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 0>;
trips {
ddr-ctrler-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
ddr-ctrler-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
};
core-cluster {
polling-delay-passive = <1000>;
polling-delay = <5000>;
thermal-sensors = <&tmu 1>;
trips {
core_cluster_alert: core-cluster-alert {
temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
core_cluster_crit: core-cluster-crit {
temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&core_cluster_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
clockgen: clocking@1300000 {
ddr: memory-controller@1080000 {
compatible = "fsl,qoriq-memory-controller";
reg = <0x0 0x1080000 0x0 0x1000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
little-endian;
};
dcfg: syscon@1e00000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd";
reg = <0x0 0x1e00000 0x0 0x10000>;
ranges = <0x0 0x0 0x1e00000 0x10000>;
little-endian;
fspi_clk: clock-controller@900 {
compatible = "fsl,ls1028a-flexspi-clk";
reg = <0x900 0x4>;
#clock-cells = <0>;
clocks = <&clockgen QORIQ_CLK_HWACCEL 0>;
clock-output-names = "fspi_clk";
};
};
rst: syscon@1e60000 {
compatible = "syscon";
reg = <0x0 0x1e60000 0x0 0x10000>;
little-endian;
};
scfg: syscon@1fc0000 {
compatible = "fsl,ls1028a-scfg", "syscon";
reg = <0x0 0x1fc0000 0x0 0x10000>;
big-endian;
};
clockgen: clock-controller@1300000 {
compatible = "fsl,ls1028a-clockgen";
reg = <0x0 0x1300000 0x0 0xa0000>;
#clock-cells = <2>;
......@@ -62,8 +243,8 @@
#size-cells = <0>;
reg = <0x0 0x2000000 0x0 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
......@@ -73,8 +254,8 @@
#size-cells = <0>;
reg = <0x0 0x2010000 0x0 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
......@@ -84,8 +265,8 @@
#size-cells = <0>;
reg = <0x0 0x2020000 0x0 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
......@@ -95,8 +276,8 @@
#size-cells = <0>;
reg = <0x0 0x2030000 0x0 0x10000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
......@@ -106,8 +287,8 @@
#size-cells = <0>;
reg = <0x0 0x2040000 0x0 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
......@@ -117,8 +298,8 @@
#size-cells = <0>;
reg = <0x0 0x2050000 0x0 0x10000>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
......@@ -128,8 +309,8 @@
#size-cells = <0>;
reg = <0x0 0x2060000 0x0 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
......@@ -139,152 +320,237 @@
#size-cells = <0>;
reg = <0x0 0x2070000 0x0 0x10000>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(4)>;
status = "disabled";
};
fspi: flexspi@20c0000 {
fspi: spi@20c0000 {
compatible = "nxp,lx2160a-fspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20c0000 0x0 0x10000>,
<0x0 0x20000000 0x0 0x10000000>;
reg-names = "fspi_base", "fspi_mmap";
clocks = <&clockgen 4 3>, <&clockgen 4 3>;
clock-names = "fspi_en", "fspi";
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&fspi_clk>, <&fspi_clk>;
clock-names = "fspi_en", "fspi";
status = "disabled";
};
dspi0: dspi@2100000 {
dspi0: spi@2100000 {
compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
spi-num-chipselects = <5>;
litte-endian;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
dmas = <&edma0 0 62>, <&edma0 0 60>;
dma-names = "tx", "rx";
spi-num-chipselects = <4>;
little-endian;
status = "disabled";
};
dspi1: dspi@2110000 {
dspi1: spi@2110000 {
compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2110000 0x0 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
spi-num-chipselects = <5>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
dmas = <&edma0 0 58>, <&edma0 0 56>;
dma-names = "tx", "rx";
spi-num-chipselects = <4>;
little-endian;
status = "disabled";
};
dspi2: dspi@2120000 {
dspi2: spi@2120000 {
compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2120000 0x0 0x10000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
spi-num-chipselects = <5>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
dmas = <&edma0 0 54>, <&edma0 0 2>;
dma-names = "tx", "rx";
spi-num-chipselects = <3>;
little-endian;
status = "disabled";
};
esdhc: esdhc@2140000 {
compatible = "fsl,esdhc";
esdhc: mmc@2140000 {
compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
reg = <0x0 0x2140000 0x0 0x10000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
big-endian;
clock-frequency = <0>; /* fixed up by bootloader */
clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
voltage-ranges = <1800 1800 3300 3300>;
sdhci,auto-cmd12;
little-endian;
bus-width = <4>;
status = "disabled";
};
esdhc1: esdhc@2150000 {
compatible = "fsl,esdhc";
esdhc1: mmc@2150000 {
compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
reg = <0x0 0x2150000 0x0 0x10000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
big-endian;
clock-frequency = <0>; /* fixed up by bootloader */
clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
voltage-ranges = <1800 1800>;
sdhci,auto-cmd12;
non-removable;
little-endian;
bus-width = <4>;
status = "disabled";
};
can0: can@2180000 {
compatible = "fsl,lx2160ar1-flexcan";
reg = <0x0 0x2180000 0x0 0x10000>;
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>,
<&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
clock-names = "ipg", "per";
status = "disabled";
};
can1: can@2190000 {
compatible = "fsl,lx2160ar1-flexcan";
reg = <0x0 0x2190000 0x0 0x10000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>,
<&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
clock-names = "ipg", "per";
status = "disabled";
};
duart0: serial@21c0500 {
device_type = "serial";
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0500 0x0 0x100>;
reg = <0x00 0x21c0500 0x0 0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
status = "disabled";
};
duart1: serial@21c0600 {
device_type = "serial";
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21c0600 0x0 0x100>;
reg = <0x00 0x21c0600 0x0 0x100>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
status = "disabled";
};
lpuart0: serial@2260000 {
compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x2260000 0x0 0x1000>;
interrupts = <0 232 0x4>;
clocks = <&sysclk>;
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
clock-names = "ipg";
dma-names = "rx","tx";
dmas = <&edma0 1 32>,
<&edma0 1 33>;
status = "disabled";
};
lpuart1: serial@2270000 {
compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x2270000 0x0 0x1000>;
interrupts = <0 233 0x4>;
clocks = <&sysclk>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
clock-names = "ipg";
dma-names = "rx","tx";
dmas = <&edma0 1 30>,
<&edma0 1 31>;
status = "disabled";
};
lpuart2: serial@2280000 {
compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x2280000 0x0 0x1000>;
interrupts = <0 234 0x4>;
clocks = <&sysclk>;
interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
clock-names = "ipg";
dma-names = "rx","tx";
dmas = <&edma0 1 28>,
<&edma0 1 29>;
status = "disabled";
};
lpuart3: serial@2290000 {
compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x2290000 0x0 0x1000>;
interrupts = <0 235 0x4>;
clocks = <&sysclk>;
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
clock-names = "ipg";
dma-names = "rx","tx";
dmas = <&edma0 1 26>,
<&edma0 1 27>;
status = "disabled";
};
lpuart4: serial@22a0000 {
compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x22a0000 0x0 0x1000>;
interrupts = <0 236 0x4>;
clocks = <&sysclk>;
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
clock-names = "ipg";
dma-names = "rx","tx";
dmas = <&edma0 1 24>,
<&edma0 1 25>;
status = "disabled";
};
lpuart5: serial@22b0000 {
compatible = "fsl,ls1028a-lpuart";
reg = <0x0 0x22b0000 0x0 0x1000>;
interrupts = <0 237 0x4>;
clocks = <&sysclk>;
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
clock-names = "ipg";
dma-names = "rx","tx";
dmas = <&edma0 1 22>,
<&edma0 1 23>;
status = "disabled";
};
edma0: dma-controller@22c0000 {
#dma-cells = <2>;
compatible = "fsl,ls1028a-edma", "fsl,vf610-edma";
reg = <0x0 0x22c0000 0x0 0x10000>,
<0x0 0x22d0000 0x0 0x10000>,
<0x0 0x22e0000 0x0 0x10000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma-tx", "edma-err";
dma-channels = <32>;
clock-names = "dmamux0", "dmamux1";
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>,
<&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
};
gpio1: gpio@2300000 {
compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
......@@ -318,28 +584,34 @@
little-endian;
};
usb0: usb3@3100000 {
usb0: usb@3100000 {
compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
status = "disabled";
snps,dis_rxdet_inp3_quirk;
snps,quirk-frame-length-adjustment = <0x20>;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
usb1: usb3@3110000 {
usb1: usb@3110000 {
compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
reg = <0x0 0x3110000 0x0 0x10000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
dr_mode = "host";
status = "disabled";
snps,dis_rxdet_inp3_quirk;
snps,quirk-frame-length-adjustment = <0x20>;
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
};
sata: sata@3200000 {
compatible = "fsl,ls1028a-ahci";
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
0x7 0x100520 0x0 0x4>; /* ecc sata addr*/
reg = <0x0 0x3200000 0x0 0x10000>,
<0x7 0x100520 0x0 0x4>;
reg-names = "ahci", "sata-ecc";
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(2)>;
status = "disabled";
};
......@@ -348,12 +620,25 @@
reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
<0x80 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
interrupt-names = "pme", "aer";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
dma-coherent;
num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */
0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
msi-parent = <&its>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
status = "disabled";
};
......@@ -362,44 +647,380 @@
reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
<0x88 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pme", "aer";
#address-cells = <3>;