Commit d274cbbc authored by Michael Walle's avatar Michael Walle Committed by Priyanka Jain
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usb: dwc3: Add frame length adjustment quirk



[backport from linux commit db2be4e9e30c6e43e48c5749d3fc74cee0a6bbb3]

Add adjust_frame_length_quirk for writing to fladj register
which adjusts (micro)frame length to value provided by
"snps,quirk-frame-length-adjustment" property thus avoiding
USB 2.0 devices to time-out over a longer run
Signed-off-by: default avatarMichael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain's avatarPriyanka Jain <priyanka.jain@nxp.com>
parent 7f79a2c2
......@@ -93,6 +93,27 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc)
return 0;
}
/*
* dwc3_frame_length_adjustment - Adjusts frame length if required
* @dwc3: Pointer to our controller context structure
* @fladj: Value of GFLADJ_30MHZ to adjust frame length
*/
static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj)
{
u32 reg;
if (dwc->revision < DWC3_REVISION_250A)
return;
if (fladj == 0)
return;
reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
reg &= ~DWC3_GFLADJ_30MHZ_MASK;
reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj;
dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
}
/**
* dwc3_free_one_event_buffer - Frees one event buffer
* @dwc: Pointer to our controller context structure
......@@ -569,6 +590,9 @@ static int dwc3_core_init(struct dwc3 *dwc)
if (ret)
goto err1;
/* Adjust Frame Length */
dwc3_frame_length_adjustment(dwc, dwc->fladj);
return 0;
err1:
......@@ -958,6 +982,8 @@ void dwc3_of_parse(struct dwc3 *dwc)
dwc->hird_threshold = hird_threshold
| (dwc->is_utmi_l1_suspend << 4);
dev_read_u32(dev, "snps,quirk-frame-length-adjustment", &dwc->fladj);
}
int dwc3_init(struct dwc3 *dwc)
......
......@@ -115,6 +115,7 @@
#define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
#define DWC3_GHWPARAMS8 0xc600
#define DWC3_GFLADJ 0xc630
/* Device Registers */
#define DWC3_DCFG 0xc700
......@@ -233,6 +234,10 @@
/* Global HWPARAMS6 Register */
#define DWC3_GHWPARAMS6_EN_FPGA (1 << 7)
/* Global Frame Length Adjustment Register */
#define DWC3_GFLADJ_30MHZ_SDBND_SEL (1 << 7)
#define DWC3_GFLADJ_30MHZ_MASK 0x3f
/* Device Configuration Register */
#define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
#define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
......@@ -812,6 +817,7 @@ struct dwc3 {
u8 test_mode_nr;
u8 lpm_nyet_threshold;
u8 hird_threshold;
u32 fladj;
unsigned delayed_status:1;
unsigned ep0_bounced:1;
......
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