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Tony Lindgren authored Aug 24, 2016 and Tom Rini committed Aug 26, 2016

If we do nand device 0 command in u-boot on a device that has NAND support
enabled but no NAND chip, we can get data abort at least on omaps.

Fix the issue by replacing the check with nand_info[dev] as
suggested by Scott Wood. The check for name existed before because before
the array-to-pointer conversion there was no way to directly test
nand_info[dev] for emptiness.
Signed-off-by: Tony Lindgren <tony@atomide.com>

Masahiro Yamada authored Aug 21, 2016 and Tom Rini committed Aug 26, 2016

Most of them are my mistakes.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Masahiro Yamada authored Aug 21, 2016 and Tom Rini committed Aug 26, 2016

This is needed to move CONFIG options for the recently-added
xtfpga_defconfig.

The tarball of the pre-built toolchain can be downloaded from:
https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Stefan Agner authored Aug 14, 2016 and Tom Rini committed Aug 26, 2016

The page table is maintained by the CPU, hence it is safe to always
align cache flush to a whole cache line size. This allows to use
mmu_page_table_flush for a single page table, e.g. when configure
only small regions through mmu_set_region_dcache_behaviour.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>

Stefan Agner authored Aug 14, 2016 and Tom Rini committed Aug 26, 2016

Add LPAE support for mmu_set_region_dcache_behaviour. The function
is in use in some LPAE capable board such TI DRA7xx or NXP i.MX 7.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>

Use a tab not 8 spaces.
Signed-off-by: Tom Rini <trini@konsulko.com>

This series moves the CONFIG_SYS_CACHELINE_SIZE.  First, in nearly all
cases we are mirroring the values used by the Linux Kernel here.  Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that we
mirror the Linux Kernel, again we are fine) it is OK to align higher.
The biggest changes here are that we always use 64 bytes for CPU_V7 even
if for example the underlying core is only 32 bytes (this mirrors
Linux).  Second, we say ARM64 uses 64 bytes not 128 (as found in the
Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large
alignment.

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Stefan Roese <sr@denx.de>
Cc: Nagendra T S <nagendra@mist...

The H3 PLL5 used for DRAM barely manages to lock to the required
frequency before DRAM controller starts, sometimes leading to wrong
delay-line calibration results.
This patch changes the PLL tuning parameters to the same values as
boot0 used, which speeds up the locking and fixes the problem.
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

When the backlight's pwm input is connected to a pwm output of the SoC,
actually use pwm to drive the backlight.

The mean reason for doing this is to fix the backlight turning off
for aprox. 1 second while the kernel is booting. This is caused by
the kernel actually using pwm to drive the backlight, so that it
can dim the backlight. First the pwm driver loads and switches the
pinmux for the pin driving the backlight's pwm input to the pwm
controller. Then about 1s later the actual backlight driver loads
and tells the pwm driver to actually update the pwm settings, which
have a power-on-reset value of "off".

An additional advantage is that this allows us to initatiate the
backlight at 80%, which is the kernel default, avoiding a brightness
change while the kernel loads.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed by: Peter Korsgaard <peter@korsgaard.com>

Add a defconfig and dts file for the Empire Electronix M712 tablet, this
is a 7" A13 tablet, with micro-usb (otg), headphone and micro-sd slots on
the outside. It uses a Goodix gt811 touchscreen controller, a RTL8188CTV
wifi chip and a DMART06 (1238a4) accelerometer.

The dts file is identical to the one submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

Sync dts files with the current (Aug 18th 2016) state of Maxime's
linux/sunxi/for-next repo.

Note this commit also updates configs/MSI_Primo81_defconfig,
adding: "# CONFIG_REQUIRE_SERIAL_CONSOLE is not set", this is necessary
because the tablet does not have a reachable uart so the dts sync
drops its serial0 alias.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

Add a defconfig and dts file for tablets using the generic inet-q972 PCB.

Tablets with this PCB feature a mini-hdmi output, micro-usb usb-host,
micro-usb usb-otg, 3.5mm headphone jack, a micro sd slot,
(mini) power-barrel and an usb wifi module.

This has been tested on a 9.7" 1024x768 qware qw tb9718-qhd tablet.

The dts files are identical to the ones submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

Simon Baatz authored Aug 10, 2016 and Stefan Roese committed Aug 26, 2016

Commit f4db6c97

 ("arm: mvebu: Add runtime detection of UART (xmodem)
boot-mode") added a change to hdr->destaddr when dynamically patching an
image for UART boot mode.  With this change, kwboot ceases to work on
Kirkwood.

Thus, let's change hdr->destaddr only when we are patching an image with
header version 1 (Orion and Kirkwood use header version 0).
Signed-off-by: Simon Baatz <gmbnomis@gmail.com>
Fixes: f4db6c97

 ("arm: mvebu: Add runtime detection of UART (xmodem) boot-mode")
Cc: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Kevin Smith <kevin.smith@elecsyscorp.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Chris Packham authored Aug 23, 2016 and Stefan Roese committed Aug 26, 2016

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Chris Packham authored Aug 22, 2016 and Stefan Roese committed Aug 26, 2016

Ensure appropriate error messages are generated. Previously all errors
indicated that the serdes was already in use. Now appropriate error
messages are given.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Chris Packham authored Aug 22, 2016 and Stefan Roese committed Aug 26, 2016

As of commit 88e34e5f

 ("spl: replace CONFIG_SPL_SPI_* with
CONFIG_SF_DEFAULT_*") these defines are not used. Remove them to avoid
confusion.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Chris Packham authored Aug 22, 2016 and Stefan Roese committed Aug 26, 2016

The NAND interface on the Armada-38x series is similar to that on the
Armada-XP. The key difference is that the NAND ECC clock ratio is
provided via the DFX Server registers instead of the Core Clock.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>

Stefan Roese authored Aug 25, 2016 and Heiko Schocher committed Aug 26, 2016

Patch f8a10ed1

 [i2c: mvtwsi: Make address length variable] accidentally
inverted the sequence of address bytes sent to the I2C device. This
patch corrects this by sending the highest byte first and the lowest
byte last again.

Tested on theadorable Armada-XP board.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Heiko Schocher <hs@denx.de>

Stephen Warren authored Aug 18, 2016 and Tom Warren committed Aug 25, 2016

In tegra20_slink.c, the set_mode() function may be executed before the
SPI bus is claimed the first time, and hence the clocks to the SPI
controller may not be running. If so, any register read/write at this
time will hang the CPU. Fix this by ensuring the clock is running as soon
as the driver is probed. This is observed on the Tegra30 Beaver board.

Apply the same clock initialization fix to all other Tegra SPI drivers so
that if set_mode() is ever implemented there, the same bug will not appear.
Note that tegra114_spi.c already operates in this fashion.

The clock manipulation code is copied from claim_bus() to probe() rather
than moved. This ensures that any calls to set_speed() take effect; the
clock can't be set once during probe and left unchanged.

Fixes: 5cb1b7b3

 ("spi: tegra20: Add support for mode selection")
Cc: Mirza Krak <mirza.krak@hostmobility.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

Stephen Warren authored Aug 22, 2016 and Tom Warren committed Aug 25, 2016

The nvidia,bpmp property is left over from an old BPMP I2C binding, and
shouldn't be present. Remove it from the SoC DT file, and update the
I2C driver not to parse it; the value wasn't used for anything any more
anyway.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

Stephen Warren authored Aug 18, 2016 and Tom Warren committed Aug 25, 2016

The Tegra SDHCI binding dictates that the reseet name for the Tegra SDHCI
clock be "sdhci" not "sdmmc", and that the clock is accessed by index
rather than by name. Fix the Tegra186 DT and MMC driver to honor this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

Stephen Warren authored Aug 18, 2016 and Tom Warren committed Aug 25, 2016

The Tegra I2C binding dictates that the clock name for the Tegra I2C clock
be "div-clk" not "i2c". Fix the Tegra186 DT and I2C driver to honor this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

Signed-off-by: Tom Rini <trini@konsulko.com>

The fs-test.sh script expected there to be a \n\r style newline at the
end of the output. This is no longer the case, so use 'tr' to remove the
\r that we get.

Fixes: (c5917b4b

 "dm: serial-uclass: Move a carriage return before a
        line feed")
Signed-off-by: Tom Rini <trini@konsulko.com>

Dongpo Li authored Aug 22, 2016 and Joe Hershberger committed Aug 22, 2016

When phy autoneg on, the link speed and duplex should be
determined by phy advertising register and
phy link partner ability register.
Check phy advertising register when geting phy link speed and
duplex if autoneg on.
Signed-off-by: Dongpo Li <lidongpo@hisilicon.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

karl beldan authored Aug 20, 2016 and Joe Hershberger committed Aug 22, 2016

The spatch series converting legacy drivers from miiphy_register to
mdio_register changed the return convention of the davinci_emac internal
MDIO accessors, making the internal code relying on it misbehaving:
no mdiodev get registered and U-Boot crashes when using net cmds in the
context of the old legacy net API.

ATM davinci_emac_initialize and cpu_eth_init don't return a proper value
in that case but fixing them would not avoid the crash.

This change is just a follow-up to the spatch pass, the MDIO accessors
of the mdiodev introduced by the spatch pass retain their proper values.
Signed-off-by: Karl Beldan <karl.beldan+oss@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Hou Zhiqiang authored Aug 19, 2016 and Joe Hershberger committed Aug 22, 2016

The QMan is not used in FMan IM mode, so no QMI enqueue or QMI
dequeue are performed.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

karl beldan authored Aug 15, 2016 and Joe Hershberger committed Aug 22, 2016

ATM when receiving a packet the whole buffer is invalidated, this change
optimizes this behaviour.
Signed-off-by: Karl Beldan <karl.beldan+oss@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>

karl beldan authored Aug 15, 2016 and Joe Hershberger committed Aug 22, 2016

check_cache_range() warns that the top boundaries are not properly
aligned when flushing or invalidating the buffers and make these
operations fail.

This gets rid of the remaining warnings:
CACHE: Misaligned operation at range
Signed-off-by: Karl Beldan <karl.beldan+oss@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>

karl beldan authored Aug 14, 2016 and Joe Hershberger committed Aug 22, 2016

ATM the rx and tx descriptors are handled as cached memory while they
lie in a dedicated RAM of the SoCs, which is an uncached area.
Removing the said dcache ops, while optimizing the logic and clarifying
the code, also gets rid of most of the check_cache_range() incurred
warnings:
CACHE: Misaligned operation at range
Signed-off-by: Karl Beldan <karl.beldan+oss@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

We use an empty hostname, so remove all the "processing" of the
known-to-be-empty hostname and just write 0's where needed.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>

Instead of always allocating a huge temporary buffer on the stack and
then memcpy()ing the result into the transmit buffer, simply figure out
where in the transmit buffer the bytes will belong and write them there
directly as each message is built.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>

Much of the information is verbose and derived directly from the
environment. Only output in debug mode. This also saves about 300 bytes
from the code size.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>

Use the same name throughout the nfs code and use the same member of the
union to avoid casts.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>

The buffer is of 32-bit elements, not bytes.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>

Instead of repeating the same large snippet for dealing with attributes
it should be shared with a helper function.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>