Commit 9a06eb80 authored by Tom Rini's avatar Tom Rini
Browse files

Merge branch '2019-07-17-ti-imports'

- Bring in the first three series that we need in order to enhance the
  TI AM65x series support and then later introduce J721E support.
parents 07a5f766 7c66eb49
......@@ -69,4 +69,78 @@
clock-frequency = <48000000>;
current-speed = <115200>;
};
main_pmx0: pinmux@11c000 {
compatible = "pinctrl-single";
reg = <0x0 0x11c000 0x0 0x2e4>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
main_pmx1: pinmux@11c2e8 {
compatible = "pinctrl-single";
reg = <0x0 0x11c2e8 0x0 0x24>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
sdhci0: sdhci@4f80000 {
compatible = "ti,am654-sdhci-5.1";
reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
power-domains = <&k3_pds 47>;
clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
clock-names = "clk_ahb", "clk_xin";
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
ti,otap-del-sel = <0x2>;
ti,trm-icp = <0x8>;
dma-coherent;
};
main_i2c0: i2c@2000000 {
compatible = "ti,am654-i2c", "ti,omap4-i2c";
reg = <0x0 0x2000000 0x0 0x100>;
interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 110 1>;
power-domains = <&k3_pds 110>;
};
main_i2c1: i2c@2010000 {
compatible = "ti,am654-i2c", "ti,omap4-i2c";
reg = <0x0 0x2010000 0x0 0x100>;
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 111 1>;
power-domains = <&k3_pds 111>;
};
main_i2c2: i2c@2020000 {
compatible = "ti,am654-i2c", "ti,omap4-i2c";
reg = <0x0 0x2020000 0x0 0x100>;
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 112 1>;
power-domains = <&k3_pds 112>;
};
main_i2c3: i2c@2030000 {
compatible = "ti,am654-i2c", "ti,omap4-i2c";
reg = <0x0 0x2030000 0x0 0x100>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 113 1>;
power-domains = <&k3_pds 113>;
};
};
......@@ -15,4 +15,15 @@
clock-frequency = <96000000>;
current-speed = <115200>;
};
mcu_i2c0: i2c@40b00000 {
compatible = "ti,am654-i2c", "ti,omap4-i2c";
reg = <0x0 0x40b00000 0x0 0x100>;
interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 114 1>;
power-domains = <&k3_pds 114>;
};
};
......@@ -34,6 +34,14 @@
};
};
wkup_pmx0: pinmux@4301c000 {
compatible = "pinctrl-single";
reg = <0x4301c000 0x118>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
wkup_uart0: serial@42300000 {
compatible = "ti,am654-uart";
reg = <0x42300000 0x100>;
......@@ -43,4 +51,15 @@
clock-frequency = <48000000>;
current-speed = <115200>;
};
wkup_i2c0: i2c@42120000 {
compatible = "ti,am654-i2c", "ti,omap4-i2c";
reg = <0x42120000 0x100>;
interrupts = <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 115 1>;
power-domains = <&k3_pds 115>;
};
};
......@@ -8,6 +8,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/k3.h>
/ {
model = "Texas Instruments K3 AM654 SoC";
......@@ -22,6 +23,12 @@
serial2 = &main_uart0;
serial3 = &main_uart1;
serial4 = &main_uart2;
i2c0 = &wkup_i2c0;
i2c1 = &mcu_i2c0;
i2c2 = &main_i2c0;
i2c3 = &main_i2c1;
i2c4 = &main_i2c2;
i2c5 = &main_i2c3;
};
chosen { };
......
......@@ -21,51 +21,21 @@
&cbass_main{
u-boot,dm-spl;
main_pmx0: pinmux@11c000 {
compatible = "pinctrl-single";
reg = <0x0 0x11c000 0x0 0x2e4>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
main_pmx1: pinmux@11c2e8 {
compatible = "pinctrl-single";
reg = <0x0 0x11c2e8 0x0 0x24>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
sdhci0: sdhci@04F80000 {
compatible = "arasan,sdhci-5.1";
reg = <0x0 0x4F80000 0x0 0x1000>,
<0x0 0x4F90000 0x0 0x400>;
clocks = <&k3_clks 47 1>;
power-domains = <&k3_pds 47>;
max-frequency = <25000000>;
};
sdhci1: sdhci@04FA0000 {
compatible = "arasan,sdhci-5.1";
compatible = "ti,am654-sdhci-5.1";
reg = <0x0 0x4FA0000 0x0 0x1000>,
<0x0 0x4FB0000 0x0 0x400>;
clocks = <&k3_clks 48 1>;
power-domains = <&k3_pds 48>;
max-frequency = <25000000>;
ti,otap-del-sel = <0x2>;
ti,trm-icp = <0x8>;
};
};
&cbass_mcu {
u-boot,dm-spl;
wkup_pmx0: pinmux@4301c000 {
compatible = "pinctrl-single";
reg = <0x0 0x4301c000 0x0 0x118>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
navss_mcu: navss-mcu {
compatible = "simple-bus";
......@@ -252,6 +222,14 @@
u-boot,dm-spl;
};
&wkup_pmx0 {
u-boot,dm-spl;
wkup_i2c0_pins_default {
u-boot,dm-spl;
};
};
&main_pmx0 {
u-boot,dm-spl;
main_uart0_pins_default: main_uart0_pins_default {
......@@ -276,7 +254,8 @@
AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
>;
u-boot,dm-spl;
};
......@@ -336,11 +315,6 @@
&sdhci0 {
u-boot,dm-spl;
status = "okay";
non-removable;
bus-width = <8>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
};
&sdhci1 {
......@@ -349,6 +323,7 @@
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
sdhci-caps-mask = <0x7 0x0>;
ti,driver-strength-ohm = <50>;
};
&mcu_cpsw {
......@@ -382,3 +357,7 @@
reg-names = "gmii-sel";
};
};
&wkup_i2c0 {
u-boot,dm-spl;
};
......@@ -6,6 +6,7 @@
/dts-v1/;
#include "k3-am654.dtsi"
#include <dt-bindings/pinctrl/k3.h>
/ {
compatible = "ti,am654-evm", "ti,am654";
......@@ -34,3 +35,52 @@
};
};
};
&main_pmx0 {
main_mmc0_pins_default: main_mmc0_pins_default {
pinctrl-single,pins = <
AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */
AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
>;
};
};
&wkup_pmx0 {
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
>;
};
};
&sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&main_mmc0_pins_default>;
bus-width = <8>;
non-removable;
ti,driver-strength-ohm = <50>;
};
&wkup_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
tca9554: gpio@38 {
compatible = "nxp,pca9554";
reg = <0x38>;
gpio-controller;
#gpio-cells = <2>;
};
};
......@@ -96,6 +96,12 @@
u-boot,dm-spl;
};
clk_200mhz: dummy_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
u-boot,dm-spl;
};
};
&dmsc {
......@@ -130,6 +136,32 @@
>;
u-boot,dm-spl;
};
wkup_i2c0_pins_default: wkup-i2c0-pins-default {
pinctrl-single,pins = <
AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */
AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */
>;
};
};
&main_pmx0 {
u-boot,dm-spl;
main_mmc0_pins_default: main_mmc0_pins_default {
pinctrl-single,pins = <
AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */
AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */
AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */
AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */
AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */
AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */
AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */
AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */
AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */
AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */
AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */
>;
};
};
&memorycontroller {
......@@ -137,3 +169,23 @@
pinctrl-names = "default";
pinctrl-0 = <&wkup_vtt_pins_default>;
};
&sdhci0 {
clock-names = "clk_xin";
clocks = <&clk_200mhz>;
/delete-property/ power-domains;
ti,driver-strength-ohm = <50>;
};
&sdhci1 {
clock-names = "clk_xin";
clocks = <&clk_200mhz>;
/delete-property/ power-domains;
ti,driver-strength-ohm = <50>;
};
&wkup_i2c0 {
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
};
......@@ -3,8 +3,6 @@
#ifndef _OMAP_I2C_H
#define _OMAP_I2C_H
#include <asm/arch/cpu.h>
#ifdef CONFIG_DM_I2C
/* Information about a GPIO bank */
......
......@@ -57,6 +57,33 @@
* For more information see 'Board Initialisation Flow in README.
*/
/*
* Macro for clearing BSS during SPL execution. Usually called during the
* relocation process for most boards before entering board_init_r(), but
* can also be done early before entering board_init_f() on plaforms that
* can afford it due to sufficient memory being available early.
*/
.macro SPL_CLEAR_BSS
ldr r0, =__bss_start /* this is auto-relocated! */
#ifdef CONFIG_USE_ARCH_MEMSET
ldr r3, =__bss_end /* this is auto-relocated! */
mov r1, #0x00000000 /* prepare zero to clear BSS */
subs r2, r3, r0 /* r2 = memset len */
bl memset
#else
ldr r1, =__bss_end /* this is auto-relocated! */
mov r2, #0x00000000 /* prepare zero to clear BSS */
clbss_l:cmp r0, r1 /* while not at end of BSS */
strlo r2, [r0] /* clear 32-bit BSS word */
addlo r0, r0, #4 /* move to next */
blo clbss_l
#endif
.endm
/*
* entry point of crt0 sequence
*/
......@@ -82,6 +109,10 @@ ENTRY(_main)
mov r9, r0
bl board_init_f_init_reserve
#if defined(CONFIG_SPL_EARLY_BSS)
SPL_CLEAR_BSS
#endif
mov r0, #0
bl board_init_f
......@@ -119,6 +150,11 @@ here:
bl c_runtime_cpu_setup /* we still call old routine here */
#endif
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_FRAMEWORK)
#if !defined(CONFIG_SPL_EARLY_BSS)
SPL_CLEAR_BSS
#endif
# ifdef CONFIG_SPL_BUILD
/* Use a DRAM stack for the rest of SPL, if requested */
bl spl_relocate_stack_gd
......@@ -126,23 +162,6 @@ here:
movne sp, r0
movne r9, r0
# endif
ldr r0, =__bss_start /* this is auto-relocated! */
#ifdef CONFIG_USE_ARCH_MEMSET
ldr r3, =__bss_end /* this is auto-relocated! */
mov r1, #0x00000000 /* prepare zero to clear BSS */
subs r2, r3, r0 /* r2 = memset len */
bl memset
#else
ldr r1, =__bss_end /* this is auto-relocated! */
mov r2, #0x00000000 /* prepare zero to clear BSS */
clbss_l:cmp r0, r1 /* while not at end of BSS */
strlo r2, [r0] /* clear 32-bit BSS word */
addlo r0, r0, #4 /* move to next */
blo clbss_l
#endif
#if ! defined(CONFIG_SPL_BUILD)
bl coloured_LED_init
......
......@@ -58,6 +58,45 @@ config SYS_K3_BOOT_CORE_ID
int
default 16
config K3_LOAD_SYSFW
bool
depends on SPL
config K3_SYSFW_IMAGE_NAME
string "File name of SYSFW firmware and configuration blob"
depends on K3_LOAD_SYSFW
default "sysfw.itb"
help
Filename of the combined System Firmware and configuration image tree
blob to be loaded when booting from a filesystem.
config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_SECT
hex "MMC sector to load SYSFW firmware and configuration blob from"
depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
default 0x3600
help
Address on the MMC to load the combined System Firmware and
configuration image tree blob from, when the MMC is being used
in raw mode. Units: MMC sectors (1 sector = 512 bytes).
config K3_SYSFW_IMAGE_MMCSD_RAW_MODE_PART
hex "MMC partition to load SYSFW firmware and configuration blob from"
depends on K3_LOAD_SYSFW && SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
default 2
help
Partition on the MMC to the combined System Firmware and configuration
image tree blob from, when the MMC is being used in raw mode.
config K3_SYSFW_IMAGE_SIZE_MAX
int "Amount of memory dynamically allocated for loading SYSFW blob"
depends on K3_LOAD_SYSFW
default 269000
help
Amount of memory (in bytes) reserved through dynamic allocation at
runtime for loading the combined System Firmware and configuration image
tree blob. Keep it as tight as possible, as this directly affects the
overall SPL memory footprint.
config SYS_K3_SPL_ATF
bool "Start Cortex-A from SPL"
depends on SPL && CPU_V7R
......
......@@ -7,4 +7,7 @@ obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
obj-$(CONFIG_ARM64) += arm64-mmu.o
obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
obj-$(CONFIG_TI_SECURE_DEVICE) += security.o
ifeq ($(CONFIG_SPL_BUILD),y)
obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o
endif
obj-y += common.o
......@@ -10,8 +10,12 @@
#include <asm/io.h>
#include <spl.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sysfw-loader.h>
#include <asm/arch/sys_proto.h>
#include "common.h"
#include <dm.h>
#include <dm/uclass-internal.h>
#include <dm/pinctrl.h>
#ifdef CONFIG_SPL_BUILD
static void mmr_unlock(u32 base, u32 partition)
......@@ -63,7 +67,7 @@ static void store_boot_index_from_rom(void)
void board_init_f(ulong dummy)
{
#if defined(CONFIG_K3_AM654_DDRSS)
#if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
struct udevice *dev;
int ret;
#endif
......@@ -83,8 +87,33 @@ void board_init_f(ulong dummy)
/* Init DM early in-order to invoke system controller */
spl_early_init();
#ifdef CONFIG_K3_LOAD_SYSFW
/*
* Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
* regardless of the result of pinctrl. Do this without probing the
* device, but instead by searching the device that would request the
* given sequence number if probed. The UART will be used by the system
* firmware (SYSFW) image for various purposes and SYSFW depends on us
* to initialize its pin settings.
*/
ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev);
if (!ret)
pinctrl_select_state(dev, "default");
/*
* Load, start up, and configure system controller firmware. Provide
* the U-Boot console init function to the SYSFW post-PM configuration
* callback hook, effectively switching on (or over) the console
* output.
*/
k3_sysfw_loader(preloader_console_init);
#else
/* Prepare console output */
preloader_console_init();
#endif
/* Perform EEPROM-based board detection */
do_board_detect();
#ifdef CONFIG_K3_AM654_DDRSS
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
......
......@@ -44,4 +44,7 @@
#define CTRLMMR_LOCK_KICK1 0x0100c
#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
/* MCU SCRATCHPAD usage */
#define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
#endif /* __ASM_ARCH_AM6_HARDWARE_H */
......@@ -12,4 +12,6 @@ u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
u32 bound);
struct ti_sci_handle *get_ti_sci_handle(void);
int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name);
int do_board_detect(void);
#endif
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* Andreas Dannenberg <dannenberg@ti.com>
*/
#ifndef _SYSFW_LOADER_H_
#define _SYSFW_LOADER_H_
void k3_sysfw_loader(void (*config_pm_done_callback)(void));
#endif
// SPDX-License-Identifier: GPL-2.0+
/*
* K3: System Firmware Loader
*
* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
* Andreas Dannenberg <dannenberg@ti.com>
*/
#include <common.h>
#include <spl.h>
#include <malloc.h>
#include <remoteproc.h>
#include <linux/soc/ti/ti_sci_protocol.h>
#include <asm/arch/sys_proto.h>