Commit 048aff6d authored by Bin Meng's avatar Bin Meng Committed by Leo Yu-Chi Liang
Browse files

riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit



All the device nodes that refer to plic0 as their interrupt parent
have 2 cells encoded in their interrupts property, but plic0 only
provides 1 cell in #interrupt-cells which is incorrect.
Signed-off-by: Bin Meng's avatarBin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen's avatarRick Chen <rick@andestech.com>
Reviewed-by: default avatarLeo Yu-Chi Liang <ycliang@andestech.com>
parent f050dd2b
...@@ -135,7 +135,7 @@ ...@@ -135,7 +135,7 @@
plic0: interrupt-controller@e4000000 { plic0: interrupt-controller@e4000000 {
compatible = "riscv,plic0"; compatible = "riscv,plic0";
#interrupt-cells = <1>; #interrupt-cells = <2>;
interrupt-controller; interrupt-controller;
reg = <0xe4000000 0x2000000>; reg = <0xe4000000 0x2000000>;
riscv,ndev=<71>; riscv,ndev=<71>;
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment