Commit 127dbec3 authored by Pali Rohár's avatar Pali Rohár Committed by Stefan Roese
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arm: a37xx: pci: Don't put link into LTSSM Recovery state during probe

During our debugging of the Aardvark driver in Linux we have discovered
that the PCIE_CORE_LINK_CTRL_STAT_REG register in fact controls standard
PCIe Link Control Register for PCIe Root Bridge. This led us to discover
that the name of the PCIE_CORE_LINK_TRAINING macro and the corresponding
comment by this macro's usage is misleading; this bit in fact controls
Retrain Link, which, according to PCIe base spec is defined as:

  A write of 1b to this bit initiates Link retraining by directing the
  Physical Layer LTSSM to the Recovery state. If the LTSSM is already in
  Recovery or Configuration, re-entering Recovery is permitted but not

Entering Recovery state is normally done from LTSSM L0, L0s and L1 states.
But since the pci-aardvark.c driver enables Link Training just a few lines
above, the controller is not in L0 ready state yet. So setting aardvark bit
PCIE_CORE_LINK_TRAINING does not actually enter Recovery state at this

Moreover, trying to enter LTSSM Recovery state without other configuration
is causing issues for some cards (e.g. Atheros AR9xxx and QCA9xxx). Since
Recovery state is not entered, these issues are not triggered.

Remove code which tries to enter LTSSM Recovery state completely.
Signed-off-by: default avatarPali Rohár <>
Reviewed-by: default avatarMarek Behún <>
Reviewed-by: Stefan Roese's avatarStefan Roese <>
parent 89be8e31
......@@ -613,11 +613,6 @@ static int pcie_advk_setup_hw(struct pcie_advk *pcie)
advk_writel(pcie, reg, PIO_CTRL);
/* Start link training */
reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
/* Wait for PCIe link up */
if (pcie_advk_wait_for_link(pcie))
return -ENXIO;
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