Commit 173c3bcd authored by Tom Rini's avatar Tom Rini
Browse files

Merge tag 'ti-v2021.10-next-v2' of https://source.denx.de/u-boot/custodians/u-boot-ti into next

- HSM re-architecture support for all K3 platforms
- AM64 USB support
- Driver model support for Davinci RTC
parents e8f720ee 5abb694d
......@@ -398,3 +398,8 @@
&sham {
status = "okay";
};
&rtc {
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};
......@@ -762,3 +762,8 @@
pinctrl-names = "default";
pinctrl-0 = <&dcan1_pins_default>;
};
&rtc {
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};
......@@ -724,3 +724,8 @@
&lcdc {
status = "okay";
};
&rtc {
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};
......@@ -122,3 +122,9 @@
&sham {
status = "okay";
};
&rtc {
clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
system-power-controller;
};
......@@ -14,7 +14,7 @@
ranges = <0x0 0x00 0x70000000 0x200000>;
atf-sram@0 {
reg = <0x0 0x1a000>;
reg = <0x1a0000 0x1c000>;
};
};
......@@ -499,6 +499,36 @@
clock-names = "gpio";
};
usbss0: cdns-usb@f900000{
compatible = "ti,am64-usb", "ti,j721e-usb";
reg = <0x00 0xf900000 0x00 0x100>;
power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 161 9>, <&k3_clks 161 1>;
clock-names = "ref", "lpm";
assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */
assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */
#address-cells = <2>;
#size-cells = <2>;
ranges;
usb0: usb@f400000{
compatible = "cdns,usb3";
reg = <0x00 0xf400000 0x00 0x10000>,
<0x00 0xf410000 0x00 0x10000>,
<0x00 0xf420000 0x00 0x10000>;
reg-names = "otg",
"xhci",
"dev";
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
interrupt-names = "host",
"peripheral",
"otg";
maximum-speed = "super-speed";
dr_mode = "otg";
};
};
main_gpio1: gpio@601000 {
compatible = "ti,j721e-gpio", "ti,keystone-gpio";
reg = <0x00 0x00601000 0x00 0x100>;
......
......@@ -50,6 +50,19 @@
u-boot,dm-spl;
};
&usb0 {
dr_mode="peripheral";
u-boot,dm-spl;
};
&usbss0 {
u-boot,dm-spl;
};
&main_usb0_pins_default {
u-boot,dm-spl;
};
&dmss {
u-boot,dm-spl;
};
......
......@@ -201,6 +201,12 @@
AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
>;
};
main_usb0_pins_default: main-usb0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
};
&main_uart0 {
......@@ -337,3 +343,15 @@
ti,driver-strength-ohm = <50>;
disable-wp;
};
&usbss0 {
ti,vbus-divider;
ti,usb2-only;
};
&usb0 {
dr_mode = "otg";
maximum-speed = "high-speed";
pinctrl-names = "default";
pinctrl-0 = <&main_usb0_pins_default>;
};
......@@ -141,6 +141,12 @@
AM64X_IOPAD(0x0030, PIN_OUTPUT_PULLUP, 7) /* (L18) OSPI0_CSN1.GPIO0_12 */
>;
};
main_usb0_pins_default: main-usb0-pins-default {
pinctrl-single,pins = <
AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
>;
};
};
&dmsc {
......@@ -201,4 +207,16 @@
/delete-property/ power-domains;
};
&usbss0 {
ti,vbus-divider;
ti,usb2-only;
};
&usb0 {
dr_mode = "otg";
maximum-speed = "high-speed";
pinctrl-names = "default";
pinctrl-0 = <&main_usb0_pins_default>;
};
#include "k3-am642-evm-u-boot.dtsi"
......@@ -35,11 +35,25 @@
u-boot,dm-spl;
ringacc@2b800000 {
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
<0x0 0x2a500000 0x0 0x40000>,
<0x0 0x28440000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
u-boot,dm-spl;
ti,dma-ring-reset-quirk;
};
dma-controller@285c0000 {
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x284c0000 0x0 0x4000>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x284a0000 0x0 0x4000>,
<0x0 0x2aa00000 0x0 0x40000>,
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
"tchanrt", "rflow";
u-boot,dm-spl;
};
};
......
......@@ -33,13 +33,39 @@
compatible = "ti,omap5430-timer";
reg = <0x0 0x40400000 0x0 0x80>;
ti,timer-alwon;
clock-frequency = <25000000>;
clock-frequency = <250000000>;
u-boot,dm-spl;
};
chipid@43000014 {
u-boot,dm-spl;
};
mcu-navss{
u-boot,dm-spl;
ringacc@2b800000 {
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
<0x0 0x2a500000 0x0 0x40000>,
<0x0 0x28440000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
u-boot,dm-spl;
};
dma-controller@285c0000 {
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x284c0000 0x0 0x4000>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x284a0000 0x0 0x4000>,
<0x0 0x2aa00000 0x0 0x40000>,
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
"tchanrt", "rflow";
u-boot,dm-spl;
};
};
};
&secure_proxy_main {
......
......@@ -6,7 +6,7 @@
/dts-v1/;
#include "k3-j7200-som-p0.dtsi"
#include "k3-j7200-ddr-evm-lp4-1600.dtsi"
#include "k3-j7200-ddr-evm-lp4-2666.dtsi"
#include "k3-j721e-ddr.dtsi"
/ {
......@@ -79,6 +79,16 @@
mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
mbox-names = "tx", "rx";
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <3>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&mcu_secproxy 21>,
<&mcu_secproxy 23>;
u-boot,dm-spl;
};
};
&dmsc {
......@@ -276,4 +286,11 @@
};
};
&mcu_ringacc {
ti,sci = <&dm_tifs>;
};
&mcu_udmap {
ti,sci = <&dm_tifs>;
};
#include "k3-j7200-common-proc-board-u-boot.dtsi"
......@@ -46,7 +46,7 @@
compatible = "ti,omap5430-timer";
reg = <0x0 0x40400000 0x0 0x80>;
ti,timer-alwon;
clock-frequency = <25000000>;
clock-frequency = <250000000>;
u-boot,dm-spl;
};
......@@ -54,10 +54,24 @@
u-boot,dm-spl;
ringacc@2b800000 {
reg = <0x0 0x2b800000 0x0 0x400000>,
<0x0 0x2b000000 0x0 0x400000>,
<0x0 0x28590000 0x0 0x100>,
<0x0 0x2a500000 0x0 0x40000>,
<0x0 0x28440000 0x0 0x40000>;
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
u-boot,dm-spl;
};
dma-controller@285c0000 {
reg = <0x0 0x285c0000 0x0 0x100>,
<0x0 0x284c0000 0x0 0x4000>,
<0x0 0x2a800000 0x0 0x40000>,
<0x0 0x284a0000 0x0 0x4000>,
<0x0 0x2aa00000 0x0 0x40000>,
<0x0 0x28400000 0x0 0x2000>;
reg-names = "gcfg", "rchan", "rchanrt", "tchan",
"tchanrt", "rflow";
u-boot,dm-spl;
};
};
......
......@@ -76,6 +76,16 @@
power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
#thermal-sensor-cells = <1>;
};
dm_tifs: dm-tifs {
compatible = "ti,j721e-dm-sci";
ti,host-id = <3>;
ti,secure-host;
mbox-names = "rx", "tx";
mboxes= <&mcu_secproxy 21>,
<&mcu_secproxy 23>;
u-boot,dm-spl;
};
};
&cbass_main {
......@@ -345,3 +355,11 @@
u-boot,dm-spl;
};
};
&mcu_ringacc {
ti,sci = <&dm_tifs>;
};
&mcu_udmap {
ti,sci = <&dm_tifs>;
};
......@@ -147,6 +147,24 @@ config SYS_K3_SPL_ATF
Enabling this will try to start Cortex-A (typically with ATF)
after SPL from R5.
config K3_ATF_LOAD_ADDR
hex "Load address of ATF image"
default 0x70000000
help
The load address for the ATF image. This value defaults to 0x70000000
if not provided in the board defconfig file.
config K3_DM_FW
bool "Separate DM firmware image"
depends on SPL && CPU_V7R && SOC_K3_J721E && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
default y
help
Enabling this will indicate that the system has separate DM
and TIFS firmware images in place, instead of a single SYSFW
firmware. Due to DM being executed on the same core as R5 SPL
bootloader, it makes RM and PM services not being available
during R5 SPL execution time.
source "board/ti/am65x/Kconfig"
source "board/ti/am64x/Kconfig"
source "board/ti/j721e/Kconfig"
......
......@@ -4,7 +4,7 @@
# Lokesh Vutla <lokeshvutla@ti.com>
obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o
obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/
obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
obj-$(CONFIG_ARM64) += arm64-mmu.o
obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
......
......@@ -8,6 +8,7 @@
*/
#include <common.h>
#include <fdt_support.h>
#include <spl.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
......@@ -106,6 +107,38 @@ void do_dt_magic(void)
}
#endif
#if CONFIG_IS_ENABLED(USB_STORAGE)
static int fixup_usb_boot(const void *fdt_blob)
{
int ret = 0;
switch (spl_boot_device()) {
case BOOT_DEVICE_USB:
/*
* If the boot mode is host, fixup the dr_mode to host
* before cdns3 bind takes place
*/
ret = fdt_find_and_setprop((void *)fdt_blob,
"/bus@f4000/cdns-usb@f900000/usb@f400000",
"dr_mode", "host", 5, 0);
if (ret)
printf("%s: fdt_find_and_setprop() failed:%d\n",
__func__, ret);
fallthrough;
default:
break;
}
return ret;
}
int fdtdec_board_setup(const void *fdt_blob)
{
/* Can use the pointer from the function parameters */
return fixup_usb_boot(fdt_blob);
}
#endif
void board_init_f(ulong dummy)
{
#if defined(CONFIG_K3_LOAD_SYSFW)
......@@ -192,8 +225,11 @@ static u32 __get_backup_bootmedia(u32 main_devstat)
case BACKUP_BOOT_DEVICE_UART:
return BOOT_DEVICE_UART;
case BACKUP_BOOT_DEVICE_USB:
return BOOT_DEVICE_USB;
case BACKUP_BOOT_DEVICE_DFU:
if (bkup_bootmode_cfg & MAIN_DEVSTAT_BACKUP_USB_MODE_MASK)
return BOOT_DEVICE_USB;
return BOOT_DEVICE_DFU;
case BACKUP_BOOT_DEVICE_ETHERNET:
return BOOT_DEVICE_ETHERNET;
......@@ -245,6 +281,12 @@ static u32 __get_primary_bootmedia(u32 main_devstat)
return BOOT_DEVICE_MMC2;
return BOOT_DEVICE_MMC1;
case BOOT_DEVICE_DFU:
if ((bootmode_cfg & MAIN_DEVSTAT_PRIMARY_USB_MODE_MASK) >>
MAIN_DEVSTAT_PRIMARY_USB_MODE_SHIFT)
return BOOT_DEVICE_USB;
return BOOT_DEVICE_DFU;
case BOOT_DEVICE_NOBOOT:
return BOOT_DEVICE_RAM;
}
......
......@@ -28,6 +28,27 @@
#include <elf.h>
#include <soc.h>
#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
enum {
IMAGE_ID_ATF,
IMAGE_ID_OPTEE,
IMAGE_ID_SPL,
IMAGE_ID_DM_FW,
IMAGE_AMT,
};
#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS)
static const char *image_os_match[IMAGE_AMT] = {
"arm-trusted-firmware",
"tee",
"U-Boot",
"DM",
};
#endif
static struct image_info fit_image_info[IMAGE_AMT];
#endif
struct ti_sci_handle *get_ti_sci_handle(void)
{
struct udevice *dev;
......@@ -107,7 +128,7 @@ int early_console_init(void)
}
#endif
#ifdef CONFIG_SYS_K3_SPL_ATF
#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
void init_env(void)
{
......@@ -181,7 +202,7 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
typedef void __noreturn (*image_entry_noargs_t)(void);
struct ti_sci_handle *ti_sci = get_ti_sci_handle();
u32 loadaddr = 0;
int ret, size;
int ret, size = 0;
/* Release all the exclusive devices held by SPL before starting ATF */
ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
......@@ -191,16 +212,22 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
panic("rproc failed to be initialized (%d)\n", ret);
init_env();
start_non_linux_remote_cores();
size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
&loadaddr);
if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
start_non_linux_remote_cores();
size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
&loadaddr);
}
/*
* It is assumed that remoteproc device 1 is the corresponding
* Cortex-A core which runs ATF. Make sure DT reflects the same.
*/
ret = rproc_load(1, spl_image->entry_point, 0x200);
if (!fit_image_info[IMAGE_ID_ATF].image_start)
fit_image_info[IMAGE_ID_ATF].image_start =
spl_image->entry_point;
ret = rproc_load(1, fit_image_info[IMAGE_ID_ATF].image_start, 0x200);
if (ret)
panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
......@@ -210,7 +237,8 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
ret = rproc_start(1);
if (ret)
panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
if (!(size > 0 && valid_elf_image(loadaddr))) {
if (!fit_image_info[IMAGE_ID_DM_FW].image_len &&
!(size > 0 && valid_elf_image(loadaddr))) {
debug("Shutting down...\n");
release_resources_for_core_shutdown();
......@@ -218,13 +246,54 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
asm volatile("wfe");
}
image_entry_noargs_t image_entry =
(image_entry_noargs_t)load_elf_image_phdr(loadaddr);
if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
loadaddr = load_elf_image_phdr(loadaddr);
} else {
loadaddr = fit_image_info[IMAGE_ID_DM_FW].image_start;
if (valid_elf_image(loadaddr))
loadaddr = load_elf_image_phdr(loadaddr);
}
debug("%s: jumping to address %x\n", __func__, loadaddr);
image_entry_noargs_t image_entry = (image_entry_noargs_t)loadaddr;
image_entry();
}
#endif
#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS)
void board_fit_image_post_process(const void *fit, int node, void **p_image,
size_t *p_size)
{
#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
int len;
int i;
const char *os;
u32 addr;
os = fdt_getprop(fit, node, "os", &len);
addr = fdt_getprop_u32_default_node(fit, node, 0, "entry", -1);
debug("%s: processing image: addr=%x, size=%d, os=%s\n", __func__,
addr, *p_size, os);
for (i = 0; i < IMAGE_AMT; i++) {
if (!strcmp(os, image_os_match[i])) {
fit_image_info[i].image_start = addr;
fit_image_info[i].image_len = *p_size;
debug("%s: matched image for ID %d\n", __func__, i);
break;
}
}
#endif
#if IS_ENABLED(CONFIG_TI_SECURE_DEVICE)
ti_secure_image_post_process(p_image, p_size);
#endif
}
#endif
#if defined(CONFIG_OF_LIBFDT)
int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name)
{
......
......@@ -28,3 +28,4 @@ void k3_sysfw_print_ver(void);
void spl_enable_dcache(void);
void mmr_unlock(phys_addr_t base, u32 partition);
bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data);
void ti_secure_image_post_process(void **p_image, size_t *p_size);
......@@ -49,6 +49,10 @@ endif
ifdef CONFIG_ARM64
ifeq ($(CONFIG_SOC_K3_J721E),)
export DM := /dev/null
endif
ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
SPL_ITS := u-boot-spl-k3_HS.its
$(SPL_ITS): export IS_HS=1
......@@ -67,6 +71,7 @@ endif
quiet_cmd_k3_mkits = MKITS $@
cmd_k3_mkits = \
$(srctree)/tools/k3_fit_atf.sh \
$(CONFIG_K3_ATF_LOAD_ADDR) \
$(patsubst %,$(obj)/dts/%.dtb,$(subst ",,$(LIST_OF_DTB))) > $@
$(SPL_ITS): FORCE
......
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