Commit 3414712b authored by Adrian Fiergolski's avatar Adrian Fiergolski Committed by Michal Simek
Browse files

arm64: zynqmp: Writing correct value to ANALOG_BUS

The default register configuration after powerup for PSSYSMON_ANALOG_BUS
register is incorrect. Hence, fix this in SPL by writing correct fixed
value. It follows UG1085 chapter 'PS SYSMON Analog_Bus' and reflects commit
sw_apps:zynq ("056ca65d44549ce27f716d423e8dfdefeee7440c")
in Xilinx:embeddedsw[1].

[1] https://github.com/Xilinx/embeddedsw

Signed-off-by: default avatarAdrian Fiergolski <adrian.fiergolski@fastree3d.com>
Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
parent e3b64bed
......@@ -19,6 +19,11 @@
#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_EN_SHIFT 0
#define ZYNQMP_CRL_APB_BOOT_PIN_CTRL_OUT_VAL_SHIFT 8
#define ZYNQMP_AMS_PS_SYSMON_BASEADDR 0XFFA50800
#define ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS ((ZYNQMP_AMS_PS_SYSMON_BASEADDR) \
+ 0x00000114)
#define ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL 0x00003210
#define PS_MODE0 BIT(0)
#define PS_MODE1 BIT(1)
#define PS_MODE2 BIT(2)
......
......@@ -287,6 +287,17 @@ int board_early_init_f(void)
if (ret)
return ret;
/*
* PS_SYSMON_ANALOG_BUS register determines mapping between SysMon
* supply sense channel to SysMon supply registers inside the IP.
* This register must be programmed to complete SysMon IP
* configuration. The default register configuration after
* power-up is incorrect. Hence, fix this by writing the
* correct value - 0x3210.
*/
writel(ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL,
ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS);
/* Delay is required for clocks to be propagated */
udelay(1000000);
#endif
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment