ppc4xx: Add initial AMCC Kilauea 405EX support

Signed-off-by: Stefan Roese <sr@denx.de>

MAINTAINERS

@@ -304,6 +304,7 @@ Stefan Roese <sr@denx.de>
 	bunbinga		PPC405EP
 	ebony			PPC440GP
 	katmai			PPC440SPe
+	kilauea			PPC405EX
 	lwmon5			PPC440EPx
 	ocotea			PPC440GX
 	p3p440			PPC440GP

MAKEALL

@@ -187,6 +187,7 @@ LIST_4xx="		\
 	JSE		\
 	KAREF		\
 	katmai		\
+	kilauea		\
 	luan		\
 	lwmon5		\
 	METROBOX	\

Makefile

@@ -1168,6 +1168,9 @@ KAREF_config: unconfig
 katmai_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx katmai amcc
 
+kilauea_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) ppc ppc4xx kilauea amcc
+
 luan_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx luan amcc
 

board/amcc/kilauea/Makefile

+#
+# (C) Copyright 2007
+# Stefan Roese, DENX Software Engineering, sr@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	= $(BOARD).o cmd_pll.o memory.o
+SOBJS	= init.o
+
+SRCS 	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend *~
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

board/amcc/kilauea/cmd_pll.c

+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * ehnus: change pll frequency.
+ * Wed Sep  5 11:45:17 CST 2007
+ * hsun@udtech.com.cn
+ */
+
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <i2c.h>
+
+#ifdef CONFIG_CMD_EEPROM
+
+#define EEPROM_CONF_OFFSET		0
+#define EEPROM_TEST_OFFSET		16
+#define EEPROM_SDSTP_PARAM		16
+
+#define PLL_NAME_MAX			12
+#define BUF_STEP			8
+
+/* eeprom_wirtes 8Byte per op. */
+#define EEPROM_ALTER_FREQ(freq)						\
+	do {								\
+		int __i;						\
+		for (__i = 0; __i < 2; __i++)				\
+			eeprom_write (CFG_I2C_EEPROM_ADDR,		\
+				      EEPROM_CONF_OFFSET + __i*BUF_STEP, \
+				      pll_select[freq],			\
+				      BUF_STEP + __i*BUF_STEP);		\
+	} while (0)
+
+#define PDEBUG
+#ifdef	PDEBUG
+#define PLL_DEBUG	pll_debug(EEPROM_CONF_OFFSET)
+#else
+#define PLL_DEBUG
+#endif
+
+typedef enum {
+	PLL_ebc20,
+	PLL_333,
+	PLL_4001,
+	PLL_4002,
+	PLL_533,
+	PLL_600,
+	PLL_666,	/* For now, kilauea can't support */
+	RCONF,
+	WTEST,
+	PLL_TOTAL
+} pll_freq_t;
+
+static const char
+pll_name[][PLL_NAME_MAX] = {
+	"PLL_ebc20",
+	"PLL_333",
+	"PLL_400@1",
+	"PLL_400@2",
+	"PLL_533",
+	"PLL_600",
+	"PLL_666",
+	"RCONF",
+	"WTEST",
+	""
+};
+
+/*
+ * ehnus:
+ */
+static uchar
+pll_select[][EEPROM_SDSTP_PARAM] = {
+	/* 0: CPU 333MHz EBC 20MHz, for test only */
+	{
+		0x8c, 0x12, 0xec, 0x12, 0x88, 0x00, 0x0a, 0x00,
+		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+	},
+
+	/* 0: 333 */
+	{
+		0x8c, 0x12, 0xec, 0x12, 0x98, 0x00, 0x0a, 0x00,
+		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+	},
+
+	/* 1: 400_266 */
+	{
+		0x8e, 0x0e, 0xe8, 0x13, 0x98, 0x00, 0x0a, 0x00,
+		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+	},
+
+	/* 2: 400 */
+	{
+		0x8e, 0x0e, 0xe8, 0x12, 0x98, 0x00, 0x0a, 0x00,
+		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+	},
+
+	/* 3: 533 */
+	{
+		0x8e, 0x43, 0x60, 0x13, 0x98, 0x00, 0x0a, 0x00,
+		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+	},
+
+	/* 4: 600 */
+	{
+		0x8d, 0x02, 0x34, 0x13, 0x98, 0x00, 0x0a, 0x00,
+		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+	},
+
+	/* 5: 666 */
+	{
+		0x8d, 0x03, 0x78, 0x13, 0x98, 0x00, 0x0a, 0x00,
+		0x40, 0x08, 0x23, 0x50, 0x00, 0x05, 0x00, 0x00
+	},
+
+	{}
+};
+
+static uchar
+testbuf[EEPROM_SDSTP_PARAM] = {
+	0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
+	0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff
+};
+
+static void
+pll_debug(int off)
+{
+	int i;
+	uchar buffer[EEPROM_SDSTP_PARAM];
+
+	memset(buffer, 0, sizeof(buffer));
+	eeprom_read(CFG_I2C_EEPROM_ADDR, off,
+		    buffer, EEPROM_SDSTP_PARAM);
+
+	printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off);
+	for (i = 0; i < EEPROM_SDSTP_PARAM; i++)
+		printf("%02x ", buffer[i]);
+	printf("\n");
+}
+
+static void
+test_write(void)
+{
+	printf("Debug: test eeprom_write ... ");
+
+	/*
+	 * Write twice, 8 bytes per write
+	 */
+	eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET,
+		      testbuf, 8);
+	eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8,
+		      testbuf, 16);
+	printf("done\n");
+
+	pll_debug(EEPROM_TEST_OFFSET);
+}
+
+int
+do_pll_alter (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	char c = '\0';
+	pll_freq_t pll_freq;
+	if (argc < 2) {
+		printf("Usage: \n%s\n", cmdtp->usage);
+		goto ret;
+	}
+
+	for (pll_freq = PLL_ebc20; pll_freq < PLL_TOTAL; pll_freq++)
+		if (!strcmp(pll_name[pll_freq], argv[1]))
+			break;
+
+	switch (pll_freq) {
+	case PLL_ebc20:
+	case PLL_333:
+	case PLL_4001:
+	case PLL_4002:
+	case PLL_533:
+	case PLL_600:
+		EEPROM_ALTER_FREQ(pll_freq);
+		break;
+
+	case PLL_666:		/* not support */
+		printf("Choose this option will result in a boot failure."
+		       "\nContinue? (Y/N): ");
+
+		c = getc(); putc('\n');
+
+		if ((c == 'y') || (c == 'Y')) {
+			EEPROM_ALTER_FREQ(pll_freq);
+			break;
+		}
+		goto ret;
+
+	case RCONF:
+		pll_debug(EEPROM_CONF_OFFSET);
+		goto ret;
+	case WTEST:
+		printf("DEBUG: write test\n");
+		test_write();
+		goto ret;
+
+	default:
+		printf("Invalid options"
+		       "\n\nUsage: \n%s\n", cmdtp->usage);
+		goto ret;
+	}
+
+	printf("PLL set to %s, "
+	       "reset the board to take effect\n", pll_name[pll_freq]);
+
+	PLL_DEBUG;
+ret:
+	return 0;
+}
+
+U_BOOT_CMD(
+	pllalter, CFG_MAXARGS, 1,        do_pll_alter,
+	"pllalter- change pll frequence \n",
+	"pllalter <selection>      - change pll frequence \n\n\
+	** New freq take effect after reset. ** \n\
+	----------------------------------------------\n\
+	PLL_ebc20: Board: AMCC 405EX(r) Evaluation Board\n\
+	\t	Same as PLL_333	\n\
+	\t	except          \n\
+	\t	EBC: 20 MHz     \n\
+	----------------------------------------------\n\
+	PLL_333: Board: AMCC 405EX(r) Evaluation Board\n\
+	\t	VCO: 666 MHz  \n\
+	\t	CPU: 333 MHz  \n\
+	\t	PLB: 166 MHz  \n\
+	\t	OPB: 83 MHz   \n\
+	\t	DDR: 83 MHz   \n\
+	------------------------------------------------\n\
+	PLL_400@1: Board: AMCC 405EX(r) Evaluation Board\n\
+	\t	VCO: 800 MHz  \n\
+	\t	CPU: 400 MHz  \n\
+	\t	PLB: 133 MHz  \n\
+	\t	OPB: 66  MHz  \n\
+	\t	DDR: 133 MHz  \n\
+	------------------------------------------------\n\
+	PLL_400@2: Board: AMCC 405EX(r) Evaluation Board\n\
+	\t	VCO: 800 MHz  \n\
+	\t	CPU: 400 MHz  \n\
+	\t	PLB: 200 MHz  \n\
+	\t	OPB: 100 MHz  \n\
+	\t	DDR: 200 MHz  \n\
+	----------------------------------------------\n\
+	PLL_533: Board: AMCC 405EX(r) Evaluation Board\n\
+	\t	VCO: 1066 MHz  \n\
+	\t	CPU: 533  MHz  \n\
+	\t	PLB: 177  MHz  \n\
+	\t	OPB: 88   MHz  \n\
+	\t	DDR: 177  MHz  \n\
+	----------------------------------------------\n\
+	PLL_600: Board: AMCC 405EX(r) Evaluation Board\n\
+	\t	VCO: 1200 MHz  \n\
+	\t	CPU: 600  MHz  \n\
+	\t	PLB: 200  MHz  \n\
+	\t	OPB: 100  MHz  \n\
+	\t	DDR: 200  MHz  \n\
+	----------------------------------------------\n\
+	PLL_666: Board: AMCC 405EX(r) Evaluation Board\n\
+	\t	VCO: 1333 MHz  \n\
+	\t	CPU: 666  MHz  \n\
+	\t	PLB: 166  MHz  \n\
+	\t	OPB: 83   MHz  \n\
+	\t	DDR: 166  MHz  \n\
+	-----------------------------------------------\n\
+	RCONF: Read current eeprom configuration.      \n\
+	-----------------------------------------------\n\
+	WTEST: Test EEPROM write with predefined values\n\
+	-----------------------------------------------\n"
+	);
+
+#endif	/* (CONFIG_COMMANDS & CFG_CMD_EEPROM) */

board/amcc/kilauea/config.mk

+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE = 0xFFFA0000

board/amcc/kilauea/init.S

+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * Based on code provided from UDTech and AMCC
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <ppc4xx.h>
+
+#include <ppc_asm.tmpl>
+#include <ppc_defs.h>
+
+#define mtsdram_as(reg, value)	 	\
+	addi    r4,0,reg	;     	\
+	mtdcr   memcfga,r4	;	\
+	addis   r4,0,value@h 	;	\
+	ori     r4,r4,value@l	;	\
+	mtdcr   memcfgd,r4	;
+
+	.globl  ext_bus_cntlr_init
+ext_bus_cntlr_init:
+
+	/*
+	 * DDR2 setup
+	 */
+
+	/* Following the DDR Core Manual, here is the initialization */
+
+	/* Step 1 */
+
+	/* Step 2 */
+
+	/* Step 3 */
+
+	/* SET SDRAM_MB0CF  base addr 00000000 - 128MB */
+	mtsdram_as(SDRAM_MB0CF, 0x00007701);		/* 8 -- 7*/
+
+	/* SET SDRAM_MB1CF - Not enabled */
+	mtsdram_as(SDRAM_MB1CF, 0x00000000);
+
+	/* SET SDRAM_MB2CF  - Not enabled */
+	mtsdram_as(SDRAM_MB2CF, 0x00000000);
+
+	/* SET SDRAM_MB3CF  - Not enabled */
+	mtsdram_as(SDRAM_MB3CF, 0x00000000);
+
+	/* SDRAM_CLKTR: Adv Addr clock by 90 deg */
+	mtsdram_as(SDRAM_CLKTR,0x80000000);
+
+	/* Refresh Time register (0x30) Refresh every 7.8125uS */
+	mtsdram_as(SDRAM_RTR, 0x06180000);
+
+	/* SDRAM_SDTR1 */
+	mtsdram_as(SDRAM_SDTR1,0x80201000);
+
+	/* SDRAM_SDTR2	*/
+	mtsdram_as(SDRAM_SDTR2,0x32204232);
+
+	/* SDRAM_SDTR3	*/
+	mtsdram_as(SDRAM_SDTR3,0x080b0d1a);
+
+	mtsdram_as(SDRAM_MMODE,    0x00000442);
+	mtsdram_as(SDRAM_MEMODE,   0x00000404);
+
+	/* SDRAM0_MCOPT1 (0X20) No ECC Gen */
+	mtsdram_as(SDRAM_MCOPT1,   0x04322000);
+
+	/* NOP */
+	mtsdram_as(SDRAM_INITPLR0,  0xa8380000);
+	/* precharge 3 DDR clock cycle */
+	mtsdram_as(SDRAM_INITPLR1,  0x81900400);
+	/* EMR2 twr = 2tck */
+	mtsdram_as(SDRAM_INITPLR2,  0x81020000);
+	/* EMR3  twr = 2tck */
+	mtsdram_as(SDRAM_INITPLR3,  0x81030000);
+	/* EMR DLL ENABLE twr = 2tck */
+	mtsdram_as(SDRAM_INITPLR4,  0x81010404);
+	/* MR w/ DLL reset
+	 * Note: 5 is CL.  May need to be changed
+	 */
+	mtsdram_as(SDRAM_INITPLR5,  0x81000542);
+	/* precharge 3 DDR clock cycle */
+	mtsdram_as(SDRAM_INITPLR6,  0x81900400);
+	/* Auto-refresh trfc = 26tck */
+	mtsdram_as(SDRAM_INITPLR7,  0x8D080000);
+	/* Auto-refresh trfc = 26tck */
+	mtsdram_as(SDRAM_INITPLR8,  0x8D080000);
+	/* Auto-refresh */
+	mtsdram_as(SDRAM_INITPLR9,  0x8D080000);
+	/* Auto-refresh */
+	mtsdram_as(SDRAM_INITPLR10, 0x8D080000);
+	/* MRS - normal operation; wait 2 cycle (set wait to tMRD) */
+	mtsdram_as(SDRAM_INITPLR11, 0x81000442);
+	mtsdram_as(SDRAM_INITPLR12, 0x81010780);
+	mtsdram_as(SDRAM_INITPLR13, 0x81010400);
+	mtsdram_as(SDRAM_INITPLR14, 0x00000000);
+	mtsdram_as(SDRAM_INITPLR15, 0x00000000);
+
+	/* SET MCIF0_CODT   Die Termination On */
+	mtsdram_as(SDRAM_CODT,      0x0080f837);
+	mtsdram_as(SDRAM_MODT0,     0x01800000);
+	mtsdram_as(SDRAM_MODT1,     0x00000000);
+
+	mtsdram_as(SDRAM_WRDTR, 0x00000000);
+
+	/* SDRAM0_MCOPT2 (0X21) Start initialization */
+	mtsdram_as(SDRAM_MCOPT2, 0x20000000);
+
+	/* Step 5 */
+	lis     r3,0x1	/* 400000 =  wait 100ms */
+	mtctr   r3
+
+pll_wait:
+	bdnz	pll_wait
+
+	/* Step 6 */
+
+	/* SDRAM_DLCR */
+	mtsdram_as(SDRAM_DLCR,0x030000a5);
+
+	/* SDRAM_RDCC */
+	mtsdram_as(SDRAM_RDCC,0x40000000);
+
+	/* SDRAM_RQDC */
+	mtsdram_as(SDRAM_RQDC,0x80000038);
+
+	/* SDRAM_RFDC */
+	mtsdram_as(SDRAM_RFDC,0x00000209);
+
+	/* Enable memory controller */
+	mtsdram_as(SDRAM_MCOPT2, 0x28000000);
+
+	blr

board/amcc/kilauea/kilauea.c

+/*
+ * (C) Copyright 2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ppc4xx.h>
+#include <ppc405.h>
+#include <libfdt.h>
+#include <asm/processor.h>
+#include <asm-ppc/io.h>
+
+#if defined(CONFIG_PCI)
+#include <pci.h>
+#include <asm/4xx_pcie.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+
+void fpga_init(void)
+{
+	/*
+	 * Set FPGA regs
+	 */
+	out32(CFG_FPGA_BASE, 0xff570cc0);
+}
+
+/*
+ * Board early initialization function
+ */
+int board_early_init_f (void)
+{
+	u32 val;
+
+	/*--------------------------------------------------------------------+
+	 | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board.
+	 +--------------------------------------------------------------------+
+	+---------------------------------------------------------------------+
+	|Interrupt| Source                            | Pol.  | Sensi.| Crit. |
+	+---------+-----------------------------------+-------+-------+-------+
+	| IRQ 00  | UART0                             | High  | Level | Non   |
+	| IRQ 01  | UART1                             | High  | Level | Non   |
+	| IRQ 02  | IIC0                              | High  | Level | Non   |
+	| IRQ 03  | TBD                               | High  | Level | Non   |
+	| IRQ 04  | TBD                               | High  | Level | Non   |
+	| IRQ 05  | EBM                               | High  | Level | Non   |
+	| IRQ 06  | BGI                               | High  | Level | Non   |
+	| IRQ 07  | IIC1                              | Rising| Edge  | Non   |
+	| IRQ 08  | SPI                               | High  | Lvl/ed| Non   |
+	| IRQ 09  | External IRQ 0 - (PCI-Express)    | pgm H | Pgm   | Non   |