Commit 70415e1e authored by Green Wan's avatar Green Wan Committed by Leo Yu-Chi Liang
Browse files

board: sifive: add HiFive Unmatched board support



Add defconfig and board support for HiFive Unmatched.
Signed-off-by: default avatarGreen Wan <green.wan@sifive.com>
Reviewed-by: Bin Meng's avatarBin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen's avatarRick Chen <rick@andestech.com>
parent 1c07b0c5
......@@ -20,6 +20,9 @@ config TARGET_QEMU_VIRT
config TARGET_SIFIVE_UNLEASHED
bool "Support SiFive Unleashed Board"
config TARGET_SIFIVE_UNMATCHED
bool "Support SiFive Unmatched Board"
config TARGET_SIPEED_MAIX
bool "Support Sipeed Maix Board"
......@@ -56,6 +59,7 @@ source "board/AndesTech/ax25-ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/sifive/unleashed/Kconfig"
source "board/sifive/unmatched/Kconfig"
source "board/sipeed/maix/Kconfig"
# platform-specific options below
......
......@@ -28,6 +28,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select SIFIVE_FU540
select ENV_IS_IN_SPI_FLASH
select BINMAN
select RESET_SIFIVE
imply CMD_DHCP
imply CMD_EXT2
imply CMD_EXT4
......
if TARGET_SIFIVE_UNMATCHED
config SYS_BOARD
default "unmatched"
config SYS_VENDOR
default "sifive"
config SYS_CPU
default "fu740"
config SYS_CONFIG_NAME
default "sifive-unmatched"
config SYS_TEXT_BASE
default 0x80200000 if SPL
default 0x80000000 if !RISCV_SMODE
default 0x80200000 if RISCV_SMODE
config SPL_TEXT_BASE
default 0x08000000
config SPL_OPENSBI_LOAD_ADDR
default 0x80000000
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SIFIVE_FU740
select SUPPORT_SPL
select RESET_SIFIVE
select BINMAN
imply CMD_DHCP
imply CMD_EXT2
imply CMD_EXT4
imply CMD_FAT
imply CMD_FS_GENERIC
imply CMD_GPT
imply PARTITION_TYPE_GUID
imply CMD_NET
imply CMD_PING
imply CMD_SF
imply DOS_PARTITION
imply EFI_PARTITION
imply IP_DYN
imply ISO_PARTITION
imply PHY_LIB
imply PHY_MSCC
imply SYSRESET
imply SYSRESET_GPIO
endif
SiFive HiFive Unmatched FU740 BOARD
M: Paul Walmsley <paul.walmsley@sifive.com>
M: Pragnesh Patel <pragnesh.patel@sifive.com>
M: Green Wan <green.wan@sifive.com>
S: Maintained
F: board/sifive/unmatched/
F: doc/board/sifive/hifive-unmatched-fu740.rst
F: include/configs/sifive-unmatched.h
F: configs/sifive_unmatched_defconfig
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (c) 2020-2021 SiFive, Inc
obj-y += unmatched.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
endif
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2020-2021 SiFive, Inc
*
* Authors:
* Pragnesh Patel <pragnesh.patel@sifive.com>
*/
#include <init.h>
#include <spl.h>
#include <misc.h>
#include <log.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <asm/gpio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/spl.h>
#define GEM_PHY_RESET SIFIVE_GENERIC_GPIO_NR(0, 12)
#define MODE_SELECT_REG 0x1000
#define MODE_SELECT_SD 0xb
#define MODE_SELECT_MASK GENMASK(3, 0)
int spl_board_init_f(void)
{
int ret;
ret = spl_soc_init();
if (ret) {
debug("HiFive Unmatched FU740 SPL init failed: %d\n", ret);
return ret;
}
/*
* GEMGXL init VSC8541 PHY reset sequence;
* leave pull-down active for 2ms
*/
udelay(2000);
ret = gpio_request(GEM_PHY_RESET, "gem_phy_reset");
if (ret) {
debug("gem_phy_reset gpio request failed: %d\n", ret);
return ret;
}
/* Set GPIO 12 (PHY NRESET) */
ret = gpio_direction_output(GEM_PHY_RESET, 1);
if (ret) {
debug("gem_phy_reset gpio direction set failed: %d\n", ret);
return ret;
}
udelay(1);
/* Reset PHY again to enter unmanaged mode */
gpio_set_value(GEM_PHY_RESET, 0);
udelay(1);
gpio_set_value(GEM_PHY_RESET, 1);
mdelay(15);
return 0;
}
u32 spl_boot_device(void)
{
u32 mode_select = readl((void *)MODE_SELECT_REG);
u32 boot_device = mode_select & MODE_SELECT_MASK;
switch (boot_device) {
case MODE_SELECT_SD:
return BOOT_DEVICE_MMC1;
default:
debug("Unsupported boot device 0x%x but trying MMC1\n",
boot_device);
return BOOT_DEVICE_MMC1;
}
}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
/* boot using first FIT config */
return 0;
}
#endif
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2020-2021, SiFive Inc
*
* Authors:
* Pragnesh Patel <pragnesh.patel@sifive.com>
*/
#include <common.h>
#include <dm.h>
#include <asm/arch/cache.h>
int board_init(void)
{
int ret;
/* enable all cache ways */
ret = cache_enable_ways();
if (ret) {
debug("%s: could not enable cache ways\n", __func__);
return ret;
}
return 0;
}
......@@ -322,7 +322,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
ARCH_ROCKCHIP || ARCH_MVEBU || ARCH_SOCFPGA || \
ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \
OMAP44XX || OMAP54XX || AM33XX || AM43XX || \
TARGET_SIFIVE_UNLEASHED
TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED
help
Use sector number for specifying U-Boot location on MMC/SD in
raw mode.
......@@ -339,7 +339,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
default 0x300 if ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || OMAP44XX || \
OMAP54XX || AM33XX || AM43XX || ARCH_K3
default 0x4000 if ARCH_ROCKCHIP
default 0x822 if TARGET_SIFIVE_UNLEASHED
default 0x822 if TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED
help
Address on the MMC to load U-Boot from, when the MMC is being used
in raw mode. Units: MMC sectors (1 sector = 512 bytes).
......
CONFIG_RISCV=y
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_DM_SPI=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="hifive-unmatched-a00"
CONFIG_TARGET_SIFIVE_UNMATCHED=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_CLK=y
CONFIG_DM_RESET=y
CONFIG_CMD_PCI=y
CONFIG_PCI=y
CONFIG_DM_PCI=y
CONFIG_PCI_PNP=y
CONFIG_PCIE_DW_SIFIVE=y
CONFIG_NVME=y
CONFIG_DM_ETH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_USB=y
CONFIG_CMD_USB=y
CONFIG_DM_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
CONFIG_CMD_PART=y
CONFIG_CMD_NVME=y
CONFIG_SYS_USB_EVENT_POLL=y
CONFIG_CMD_GPT=y
CONFIG_CMD_GPT_RENAME=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_MEMINFO=y
CONFIG_CMD_I2C=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_OCORES=y
CONFIG_CLK_SIFIVE_PRCI=y
CONFIG_DM_PWM=y
CONFIG_PWM_SIFIVE=y
CONFIG_CMD_PWM=y
CONFIG_SPL_USE_ARCH_MEMMOVE=n
......@@ -7,3 +7,4 @@ SiFive
:maxdepth: 2
unleashed
unmatched
This diff is collapsed.
......@@ -166,7 +166,7 @@ config RESET_IPQ419
config RESET_SIFIVE
bool "Reset Driver for SiFive SoC's"
depends on DM_RESET && CLK_SIFIVE_PRCI && TARGET_SIFIVE_UNLEASHED
depends on DM_RESET && CLK_SIFIVE_PRCI && (TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED)
default y
help
PRCI module within SiFive SoC's provides mechanism to reset
......
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2020-2021 SiFive, Inc
*
* Authors:
* Pragnesh Patel <pragnesh.patel@sifive.com>
*/
#ifndef __SIFIVE_UNMATCHED_H
#define __SIFIVE_UNMATCHED_H
#include <linux/sizes.h>
#ifdef CONFIG_SPL
#define CONFIG_SPL_MAX_SIZE 0x00100000
#define CONFIG_SPL_BSS_START_ADDR 0x85000000
#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
CONFIG_SPL_BSS_MAX_SIZE)
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
#define CONFIG_SPL_STACK (0x08000000 + 0x001D0000 - \
GENERATED_GBL_DATA_SIZE)
#endif
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M)
#define CONFIG_SYS_MALLOC_LEN SZ_8M
#define CONFIG_SYS_BOOTM_LEN SZ_64M
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit resources */
#define CONFIG_SYS_CACHELINE_SIZE 64
/* Environment options */
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \
func(NVME, nvme, 0) \
func(USB, usb, 0) \
func(MMC, mmc, 0) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#define TYPE_GUID_LOADER1 "5B193300-FC78-40CD-8002-E86C45580B47"
#define TYPE_GUID_LOADER2 "2E54B353-1271-4842-806F-E436D6AF6985"
#define TYPE_GUID_SYSTEM "0FC63DAF-8483-4772-8E79-3D69D8477DE4"
#define PARTS_DEFAULT \
"name=loader1,start=17K,size=1M,type=${type_guid_gpt_loader1};" \
"name=loader2,size=4MB,type=${type_guid_gpt_loader2};" \
"name=system,size=-,bootable,type=${type_guid_gpt_system};"
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_addr_r=0x84000000\0" \
"fdt_addr_r=0x88000000\0" \
"scriptaddr=0x88100000\0" \
"pxefile_addr_r=0x88200000\0" \
"ramdisk_addr_r=0x88300000\0" \
"kernel_comp_addr_r=0x90000000\0" \
"kernel_comp_size=0x4000000\0" \
"type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \
"type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
"type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
"partitions=" PARTS_DEFAULT "\0" \
BOOTENV
#define CONFIG_PREBOOT \
"setenv fdt_addr ${fdtcontroladdr};" \
"fdt addr ${fdtcontroladdr};"
#endif /* CONFIG_SPL_BUILD */
#endif /* __SIFIVE_UNMATCHED_H */
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