Commit 756f586a authored by wdenk's avatar wdenk
Browse files

* Patch by Yusdi Santoso, 22 Oct 2004:

  - Add support for HIDDEN_DRAGON board
  - fix endianess problem in driver/rtl1839.c

* Patch by Allen Curtis, 21 Oct 2004:
  support multiple serial ports
parent b1bf6f2c
......@@ -2,6 +2,13 @@
Changes for U-Boot 1.1.3:
======================================================================
* Patch by Yusdi Santoso, 22 Oct 2004:
- Add support for HIDDEN_DRAGON board
- fix endianess problem in driver/rtl1839.c
* Patch by Allen Curtis, 21 Oct 2004:
support multiple serial ports
* Patch by Richard Klingler, 03 Apr 2005:
Add call to eth_halt() in net/net.c when called functions fail
after eth_init() has been called.
......
......@@ -302,6 +302,10 @@ Dan Malek <dan@embeddededge.com>
STxGP3 MPC85xx
Yusdi Santoso <yusdi_santoso@adaptec.com>
HIDDEN_DRAGON MPC8241/MPC8245
-------------------------------------------------------------------------
Unknown / orphaned boards:
......
......@@ -86,9 +86,10 @@ LIST_8220=" \
LIST_824x=" \
A3000 BMW CPC45 CU824 \
debris eXalion MOUSSE MUSENKI \
MVBLUE OXC PN62 Sandpoint8240 \
Sandpoint8245 SL8245 utx8245 sbc8240 \
debris eXalion HIDDEN_DRAGON MOUSSE \
MUSENKI MVBLUE OXC PN62 \
Sandpoint8240 Sandpoint8245 SL8245 utx8245 \
sbc8240 \
"
#########################################################################
......
......@@ -900,6 +900,9 @@ debris_config: unconfig
eXalion_config: unconfig
@./mkconfig $(@:_config=) ppc mpc824x eXalion
HIDDEN_DRAGON_config: unconfig
@./mkconfig $(@:_config=) ppc mpc824x hidden_dragon
MOUSSE_config: unconfig
@./mkconfig $(@:_config=) ppc mpc824x mousse
......
#
# (C) Copyright 2000-2005
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
#########################################################################
.depend: Makefile $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################
U-Boot for Hidden Dragon board
------------------------------
Hidden Dragon is a MPC824x-based board by Motorola. For the most
part it is similar to Sandpoint8245 board. So unless otherwise
mentioned, the codes in this directory are adapted from ../sandpoint
directory.
Apparently there are very few of this board out there. Even Motorola
website does not have any info on it.
RAM:
start = 0x0000 0000
size = 0x0200 0000 (32 MB)
Flash:
BANK ONE:
start = 0xFFE0 0000
size = 0x0020 0000 (2 MB)
flash chip = 29LV160TE (1x16 Mbits or 2x8 Mbits)
flash sectors = 16K, 2x8K, 32K, 31x64K
BANK TWO:
NONE
The processor interrupt vectors reside on the first 256 bytes
starting from address 0xFFF00000. The "reset vector" (first
instruction executed after reset) is located on 0xFFF0 0100.
U-Boot is configured to reside in flash starting at the address of
0xFFF00000. The environment space is located in flash separately from
U-Boot, at the second sector of the first flash bank, starting from
0xFFE04000 until 0xFFE06000 (8KB).
Network:
- RTL8139 chip on the base board (SUPPORTED)
- RTL8129 chip on the processor board (NOT SUPPORTED)
Serial:
- Two NS16550 compatible UART on the processor board (SUPPORTED)
- One NS16550 compatible UART on the base board (UNTESTED)
Misc:
VIA686A PCI SuperIO peripheral controller
- 2 USB ports (UNTESTED)
- 2 PS2 ports (UNTESTED)
- Parallel port (UNTESTED)
- IDE & floppy interface (UNTESTED)
S3 Savage4 video card (UNTESTED)
TODO:
-----
- Support for the VIA686A based peripherals
- The RTL8139 driver frequently gives rx error.
- Support for RTL8129 network controller. (Why is the support removed from
rtl8139.c driver?)
(C) Copyright 2004
Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
#
# (C) Copyright 2000-2005
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# Hidden Dragon boards
#
TEXT_BASE = 0xFFF00000
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE)
/*
* (C) Copyright 2001
* Thomas Koeller, tkoeller@gmx.net
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASSEMBLY__
#define __ASSEMBLY__ 1
#endif
#include <config.h>
#include <asm/processor.h>
#include <mpc824x.h>
#include <ppc_asm.tmpl>
#if defined(USE_DINK32)
/* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */
#define MCCR1VAL ((CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
#else
#define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT)
#endif
.text
/* Values to program into memory controller registers */
tbl: .long MCCR1, MCCR1VAL
.long MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT
.long MCCR3
.long (((CFG_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
(CFG_REFREC << MCCR3_REFREC_SHIFT) | \
(CFG_RDLAT << MCCR3_RDLAT_SHIFT)
.long MCCR4
.long (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
(CFG_REGISTERD_TYPE_BUFFER << 20) | \
(((CFG_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
((CFG_SDMODE_CAS_LAT << 4) | (CFG_SDMODE_WRAP << 3) | \
(CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
(CFG_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
((CFG_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
.long MSAR1
.long (((CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
(((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
(((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
(((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
.long EMSAR1
.long (((CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
(((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
(((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
(((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
.long MSAR2
.long (((CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
(((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
(((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
(((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
.long EMSAR2
.long (((CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
(((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
(((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
(((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
.long MEAR1
.long (((CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
(((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
(((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
(((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
.long EMEAR1
.long (((CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
(((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
(((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
(((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
.long MEAR2
.long (((CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
(((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
(((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
(((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
.long EMEAR2
.long (((CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
(((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
(((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
(((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
.long 0
/*
* Early CPU initialization. Set up memory controller, so we can access any RAM at all. This
* must be done in assembly, since we have no stack at this point.
*/
.global early_init_f
early_init_f:
mflr r10
/* basic memory controller configuration */
lis r3, CONFIG_ADDR_HIGH
lis r4, CONFIG_DATA_HIGH
bl lab
lab: mflr r5
lwzu r0, tbl - lab(r5)
loop: lwz r1, 4(r5)
stwbrx r0, 0, r3
eieio
stwbrx r1, 0, r4
eieio
lwzu r0, 8(r5)
cmpli cr0, 0, r0, 0
bne cr0, loop
/* set bank enable bits */
lis r0, MBER@h
ori r0, 0, MBER@l
li r1, CFG_BANK_ENABLE
stwbrx r0, 0, r3
eieio
stb r1, 0(r4)
eieio
/* delay loop */
lis r0, 0x0003
mtctr r0
delay: bdnz delay
/* enable memory controller */
lis r0, MCCR1@h
ori r0, 0, MCCR1@l
stwbrx r0, 0, r3
eieio
lwbrx r0, 0, r4
oris r0, 0, MCCR1_MEMGO@h
stwbrx r0, 0, r4
eieio
/* set up stack pointer */
lis r1, CFG_INIT_SP_OFFSET@h
ori r1, r1, CFG_INIT_SP_OFFSET@l
mtlr r10
blr
/*
* (C) Copyright 2004
* Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
*
* (C) Copyright 2000-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc824x.h>
#include <asm/processor.h>
#include <asm/pci_io.h>
#include <w83c553f.h>
#define ROM_CS0_START 0xFF800000
#define ROM_CS1_START 0xFF000000
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
#if defined(CFG_ENV_IS_IN_FLASH)
# ifndef CFG_ENV_ADDR
# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
# endif
# ifndef CFG_ENV_SIZE
# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
# endif
# ifndef CFG_ENV_SECT_SIZE
# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
# endif
#endif
/*-----------------------------------------------------------------------
* Functions
*/
static int write_word (flash_info_t *info, ulong dest, ulong data);
/*flash command address offsets*/
#define ADDR0 (0xAAA)
#define ADDR1 (0x555)
#define ADDR3 (0x001)
#define FLASH_WORD_SIZE unsigned char
/*-----------------------------------------------------------------------
*/
static unsigned long flash_id (unsigned char mfct, unsigned char chip)
__attribute__ ((const));
typedef struct {
FLASH_WORD_SIZE extval;
unsigned short intval;
} map_entry;
static unsigned long flash_id (unsigned char mfct, unsigned char chip)
{
static const map_entry mfct_map[] = {
{(FLASH_WORD_SIZE) AMD_MANUFACT,
(unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)},
{(FLASH_WORD_SIZE) FUJ_MANUFACT,
(unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)},
{(FLASH_WORD_SIZE) STM_MANUFACT,
(unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)},
{(FLASH_WORD_SIZE) MT_MANUFACT,
(unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)},
{(FLASH_WORD_SIZE) INTEL_MANUFACT,
(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)},
{(FLASH_WORD_SIZE) INTEL_ALT_MANU,
(unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}
};
static const map_entry chip_map[] = {
{AMD_ID_F040B, FLASH_AM040},
{(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB}
};
const map_entry *p;
unsigned long result = FLASH_UNKNOWN;
/* find chip id */
for (p = &chip_map[0];
p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++)
if (p->extval == chip) {
result = FLASH_VENDMASK | p->intval;
break;
}
/* find vendor id */
for (p = &mfct_map[0];
p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++)
if (p->extval == mfct) {
result &= ~FLASH_VENDMASK;
result |= (unsigned long) p->intval << 16;
break;
}
return result;
}
unsigned long flash_init (void)
{
unsigned long i;
unsigned char j;
static const ulong flash_banks[] = CFG_FLASH_BANKS;
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
flash_info_t *const pflinfo = &flash_info[i];
pflinfo->flash_id = FLASH_UNKNOWN;
pflinfo->size = 0;
pflinfo->sector_count = 0;
}
/* Enable writes to Hidden Dragon flash */
{
register unsigned char temp;
CONFIG_READ_BYTE (CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR,
temp);
temp &= ~0x20; /* clear BIOSWP bit */
CONFIG_WRITE_BYTE (CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR,
temp);
}
for (i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) {
flash_info_t *const pflinfo = &flash_info[i];
const unsigned long base_address = flash_banks[i];
volatile FLASH_WORD_SIZE *const flash =
(FLASH_WORD_SIZE *) base_address;
flash[0xAAA << (3 * i)] = 0xaa;
flash[0x555 << (3 * i)] = 0x55;
flash[0xAAA << (3 * i)] = 0x90;
__asm__ __volatile__ ("sync");
pflinfo->flash_id =
flash_id (flash[0x0], flash[0x2 + 14 * i]);
switch (pflinfo->flash_id & FLASH_TYPEMASK) {
case FLASH_AM040:
pflinfo->size = 0x00080000;
pflinfo->sector_count = 8;
for (j = 0; j < 8; j++) {
pflinfo->start[j] =
base_address + 0x00010000 * j;
pflinfo->protect[j] = flash[(j << 16) | 0x2];
}
break;
case FLASH_STM800AB:
pflinfo->size = 0x00100000;
pflinfo->sector_count = 19;
pflinfo->start[0] = base_address;
pflinfo->start[1] = base_address + 0x4000;
pflinfo->start[2] = base_address + 0x6000;
pflinfo->start[3] = base_address + 0x8000;
for (j = 1; j < 16; j++) {
pflinfo->start[j + 3] =
base_address + 0x00010000 * j;
}
break;
default:
/* The chip used is not listed in flash_id
TODO: Change this to explicitly detect the flash type
*/
{
int sector_addr = base_address;
pflinfo->size = 0x00200000;
pflinfo->sector_count = 35;
pflinfo->start[0] = sector_addr;
sector_addr += 0x4000; /* 16K */
pflinfo->start[1] = sector_addr;
sector_addr += 0x2000; /* 8K */
pflinfo->start[2] = sector_addr;
sector_addr += 0x2000; /* 8K */
pflinfo->start[3] = sector_addr;
sector_addr += 0x8000; /* 32K */
for (j = 4; j < 35; j++) {
pflinfo->start[j] = sector_addr;
sector_addr += 0x10000; /* 64K */
}
}
break;
}
/* Protect monitor and environment sectors
*/
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
flash_protect (FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + monitor_flash_len - 1,
&flash_info[0]);
#endif
#if (CFG_ENV_IS_IN_FLASH == 1) && defined(CFG_ENV_ADDR)
flash_protect (FLAG_PROTECT_SET,
CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
&flash_info[0]);
#endif
/* reset device to read mode */
flash[0x0000] = 0xf0;
__asm__ __volatile__ ("sync");
}
/* only have 1 bank */
return flash_info[0].size;
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t * info)
{
static const char unk[] = "Unknown";
const char *mfct = unk, *type = unk;
unsigned int i;
if (info->flash_id != FLASH_UNKNOWN) {
switch (info->flash_id & FLASH_VENDMASK) {
case FLASH_MAN_AMD:
mfct = "AMD";
break;
case FLASH_MAN_FUJ:
mfct = "FUJITSU";
break;
case FLASH_MAN_STM:
mfct = "STM";
break;
case FLASH_MAN_SST:
mfct = "SST";
break;
case FLASH_MAN_BM:
mfct = "Bright Microelectonics";
break;
case FLASH_MAN_INTEL:
mfct = "Intel";
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case FLASH_AM040:
type = "AM29F040B (512K * 8, uniform sector size)";
break;
case FLASH_AM400B:
type = "AM29LV400B (4 Mbit, bottom boot sect)";
break;
case FLASH_AM400T:
type = "AM29LV400T (4 Mbit, top boot sector)";
break;
case FLASH_AM800B:
type = "AM29LV800B (8 Mbit, bottom boot sect)";
break;
case FLASH_AM800T:
type = "AM29LV800T (8 Mbit, top boot sector)";
break;
case FLASH_AM160T:
type = "AM29LV160T (16 Mbit, top boot sector)";
break;