Commit 862e2e75 authored by Lukas Auer's avatar Lukas Auer Committed by Andes
Browse files

riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I



RISC-V defines the base integer instruction sets as RV32I and RV64I.
Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to
match this convention.
Signed-off-by: default avatarLukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng's avatarBin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen's avatarRick Chen <rick@andestech.com>
parent 17f2ffea
......@@ -20,20 +20,20 @@ source "board/AndesTech/ax25-ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
choice
prompt "CPU selection"
default CPU_RISCV_32
prompt "Base ISA"
default ARCH_RV32I
config CPU_RISCV_32
bool "RISC-V 32-bit"
config ARCH_RV32I
bool "RV32I"
select 32BIT
help
Choose this option to build an U-Boot for RISCV32 architecture.
Choose this option to target the RV32I base integer instruction set.
config CPU_RISCV_64
bool "RISC-V 64-bit"
config ARCH_RV64I
bool "RV64I"
select 64BIT
help
Choose this option to build an U-Boot for RISCV64 architecture.
Choose this option to target the RV64I base integer instruction set.
endchoice
......
......@@ -6,7 +6,7 @@
#include <config.h>
#include <linux/linkage.h>
#ifdef CONFIG_CPU_RISCV_64
#ifdef CONFIG_ARCH_RV64I
#define STORE_IDX(reg, idx) sd reg, (idx*8)(a0)
#define LOAD_IDX(reg, idx) ld reg, (idx*8)(a0)
#else
......
CONFIG_RISCV=y
CONFIG_SYS_TEXT_BASE=0x00000000
CONFIG_TARGET_AX25_AE350=y
CONFIG_CPU_RISCV_64=y
CONFIG_ARCH_RV64I=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_FIT=y
......
CONFIG_RISCV=y
CONFIG_TARGET_QEMU_VIRT=y
CONFIG_CPU_RISCV_64=y
CONFIG_ARCH_RV64I=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
......
......@@ -99,9 +99,9 @@
#define BOOTEFI_NAME "bootia32.efi"
#elif defined(CONFIG_X86_RUN_64BIT)
#define BOOTEFI_NAME "bootx64.efi"
#elif defined(CONFIG_CPU_RISCV_32)
#elif defined(CONFIG_ARCH_RV32I)
#define BOOTEFI_NAME "bootriscv32.efi"
#elif defined(CONFIG_CPU_RISCV_64)
#elif defined(CONFIG_ARCH_RV64I)
#define BOOTEFI_NAME "bootriscv64.efi"
#endif
#endif
......@@ -257,10 +257,10 @@
#elif defined(__i386__)
#define BOOTENV_EFI_PXE_ARCH "0x6"
#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00006:UNDI:003000"
#elif defined(CONFIG_CPU_RISCV_32) || ((defined(__riscv) && __riscv_xlen == 32))
#elif defined(CONFIG_ARCH_RV32I) || ((defined(__riscv) && __riscv_xlen == 32))
#define BOOTENV_EFI_PXE_ARCH "0x19"
#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00025:UNDI:003000"
#elif defined(CONFIG_CPU_RISCV_64) || ((defined(__riscv) && __riscv_xlen == 64))
#elif defined(CONFIG_ARCH_RV64I) || ((defined(__riscv) && __riscv_xlen == 64))
#define BOOTENV_EFI_PXE_ARCH "0x1b"
#define BOOTENV_EFI_PXE_VCI "PXEClient:Arch:00027:UNDI:003000"
#elif defined(CONFIG_SANDBOX)
......
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