Commit 931da93e authored by wdenk's avatar wdenk
Browse files

Add test tool to exercise SDRAM accesses in burst mode

(as standalone program, MPC8xx/PowerPC only)
parent 412babe3
......@@ -2,6 +2,9 @@
Changes for U-Boot 1.1.3:
======================================================================
* Add test tool to exercise SDRAM accesses in burst mode
(as standalone program, MPC8xx/PowerPC only)
* Increase CFG_MONITOR_LEN for Rattler board to match actual code
size.
......
......@@ -58,6 +58,11 @@ include $(TOPDIR)/config.mk
SREC = hello_world.srec
BIN = hello_world.bin hello_world
ifeq ($(ARCH),ppc)
SREC = test_burst.srec
BIN = test_burst.bin test_burst
endif
ifeq ($(ARCH),i386)
SREC += 82559_eeprom.srec
BIN += 82559_eeprom.bin 82559_eeprom
......@@ -96,6 +101,7 @@ LIB = libstubs.a
LIBAOBJS=
ifeq ($(ARCH),ppc)
LIBAOBJS+= $(ARCH)_longjmp.o $(ARCH)_setjmp.o
LIBAOBJS+= test_burst_lib.o
endif
LIBCOBJS= stubs.o
LIBOBJS = $(LIBAOBJS) $(LIBCOBJS)
......
/*
* (C) Copyright 2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* The test exercises SDRAM accesses in burst mode
*/
#include <common.h>
#include <exports.h>
#include <commproc.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <serial.h>
#include <watchdog.h>
#include "test_burst.h"
/* 8 MB test region of physical RAM */
#define TEST_PADDR 0x00800000
/* The uncached virtual region */
#define TEST_VADDR_NC 0x00800000
/* The cached virtual region */
#define TEST_VADDR_C 0x01000000
/* When an error is detected, the address where the error has been found,
and also the current and the expected data will be written to
the following flash address
*/
#define TEST_FLASH_ADDR 0x40100000
static void test_prepare (void);
static int test_burst_start (unsigned long size, unsigned long pattern);
static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached);
static int test_mmu_is_on(void);
static void test_desc(unsigned long size);
static void test_error(char * step, volatile void * addr, unsigned long val, unsigned long pattern);
static void signal_start(void);
static void signal_error(void);
static void test_usage(void);
static unsigned long test_pattern [] = {
0x00000000,
0xffffffff,
0x55555555,
0xaaaaaaaa,
};
int test_burst (int argc, char *argv[])
{
unsigned long size = CACHE_LINE_SIZE;
int res;
int i;
if (argc == 2) {
char * d;
for (size = 0, d = argv[1]; *d >= '0' && *d <= '9'; d++) {
size *= 10;
size += *d - '0';
}
if (size == 0 || *d) {
test_usage();
return 1;
}
} else if (argc > 2) {
test_usage();
return 1;
}
size += (CACHE_LINE_SIZE - 1);
size &= ~(CACHE_LINE_SIZE - 1);
if (!test_mmu_is_on()) {
test_prepare();
}
test_desc(size);
for (i = 0; i < sizeof(test_pattern) / sizeof(test_pattern[0]); i++) {
res = test_burst_start(size, test_pattern[i]);
if (res != 0) {
goto Done;
}
}
Done:
return res;
}
static void test_prepare (void)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
printf ("\n");
caches_init();
disable_interrupts();
mmu_init();
printf ("Interrupts are disabled\n");
printf ("I-Cache is ON\n");
printf ("D-Cache is ON\n");
printf ("MMU is ON\n");
printf ("\n");
test_map_8M (TEST_PADDR, TEST_VADDR_NC, 0);
test_map_8M (TEST_PADDR, TEST_VADDR_C, 1);
test_map_8M (TEST_FLASH_ADDR & 0xFF800000, TEST_FLASH_ADDR & 0xFF800000, 0);
/* Configure PD.8 and PD.9 as general purpose output */
immr->im_ioport.iop_pdpar &= ~0x00C0;
immr->im_ioport.iop_pddir |= 0x00C0;
}
static int test_burst_start (unsigned long size, unsigned long pattern)
{
volatile unsigned long * vaddr_c = (unsigned long *)TEST_VADDR_C;
volatile unsigned long * vaddr_nc = (unsigned long *)TEST_VADDR_NC;
int i, n;
int res = 1;
printf ("Test pattern %08x ...", pattern);
n = size / 4;
for (i = 0; i < n; i ++) {
vaddr_c [i] = pattern;
}
signal_start();
flush_dcache_range((unsigned long)vaddr_c, (unsigned long)(vaddr_c + n) - 1);
for (i = 0; i < n; i ++) {
register unsigned long tmp = vaddr_nc [i];
if (tmp != pattern) {
test_error("2a", vaddr_nc + i, tmp, pattern);
goto Done;
}
}
for (i = 0; i < n; i ++) {
register unsigned long tmp = vaddr_c [i];
if (tmp != pattern) {
test_error("2b", vaddr_c + i, tmp, pattern);
goto Done;
}
}
for (i = 0; i < n; i ++) {
vaddr_nc [i] = pattern;
}
for (i = 0; i < n; i ++) {
register unsigned long tmp = vaddr_nc [i];
if (tmp != pattern) {
test_error("3a", vaddr_nc + i, tmp, pattern);
goto Done;
}
}
signal_start();
for (i = 0; i < n; i ++) {
register unsigned long tmp = vaddr_c [i];
if (tmp != pattern) {
test_error("3b", vaddr_c + i, tmp, pattern);
goto Done;
}
}
res = 0;
Done:
printf(" %s\n", res == 0 ? "OK" : "");
return res;
}
static void test_map_8M (unsigned long paddr, unsigned long vaddr, int cached)
{
mtspr (MD_EPN, (vaddr & 0xFFFFFC00) | MI_EVALID);
mtspr (MD_TWC, MI_PS8MEG | MI_SVALID);
mtspr (MD_RPN, (paddr & 0xFFFFF000) | MI_BOOTINIT | (cached ? 0 : 2));
mtspr (MD_AP, MI_Kp);
}
static int test_mmu_is_on(void)
{
unsigned long msr;
asm volatile("mfmsr %0" : "=r" (msr) :);
return msr & MSR_DR;
}
static void test_desc(unsigned long size)
{
printf(
"The following tests will be conducted:\n"
"1) Map %d-byte region of physical RAM at 0x%08x\n"
" into two virtual regions:\n"
" one cached at 0x%08x and\n"
" the the other uncached at 0x%08x.\n",
size, TEST_PADDR, TEST_VADDR_NC, TEST_VADDR_C);
puts(
"2) Fill the cached region with a pattern, and flush the cache\n"
"2a) Check the uncached region to match the pattern\n"
"2b) Check the cached region to match the pattern\n"
"3) Fill the uncached region with a pattern\n"
"3a) Check the cached region to match the pattern\n"
"3b) Check the uncached region to match the pattern\n"
"2b) Change the patterns and go to step 2\n"
"\n"
);
}
static void test_error(
char * step, volatile void * addr, unsigned long val, unsigned long pattern)
{
volatile unsigned long * p = (void *)TEST_FLASH_ADDR;
signal_error();
p[0] = (unsigned long)addr;
p[1] = val;
p[2] = pattern;
printf ("\nError at step %s, addr %08x: read %08x, pattern %08x",
step, addr, val, pattern);
}
static void signal_start(void)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
if (immr->im_ioport.iop_pddat & 0x0080) {
immr->im_ioport.iop_pddat &= ~0x0080;
} else {
immr->im_ioport.iop_pddat |= 0x0080;
}
}
static void signal_error(void)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
if (immr->im_ioport.iop_pddat & 0x0040) {
immr->im_ioport.iop_pddat &= ~0x0040;
} else {
immr->im_ioport.iop_pddat |= 0x0040;
}
}
static void test_usage(void)
{
printf("Usage: go 0x40004 [size]\n");
}
/*
* (C) Copyright 2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _TEST_BURST_H
#define _TEST_BURST_H
/* Cache line size */
#define CACHE_LINE_SIZE 16
/* Binary logarithm of the cache line size */
#define LG_CACHE_LINE_SIZE 4
#ifndef __ASSEMBLY__
extern void mmu_init(void);
extern void caches_init(void);
extern void flush_dcache_range(unsigned long start, unsigned long stop);
#endif
#endif /* _TEST_BURST_H */
/*
* (C) Copyright 2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <ppc_asm.tmpl>
#include <ppc_defs.h>
#include <asm/cache.h>
#include <asm/mmu.h>
#include "test_burst.h"
.text
/*
* void mmu_init(void);
*
* This function turns the MMU on
*
* Three 8 MByte regions are mapped 1:1, uncached
* - SDRAM lower 8 MByte
* - SDRAM higher 8 MByte
* - IMMR
*/
.global mmu_init
mmu_init:
tlbia /* Invalidate all TLB entries */
li r8, 0
mtspr MI_CTR, r8 /* Set instruction control to zero */
lis r8, MD_RESETVAL@h
mtspr MD_CTR, r8 /* Set data TLB control */
/* Now map the lower 8 Meg into the TLBs. For this quick hack,
* we can load the instruction and data TLB registers with the
* same values.
*/
li r8, MI_EVALID /* Create EPN for address 0 */
mtspr MI_EPN, r8
mtspr MD_EPN, r8
li r8, MI_PS8MEG /* Set 8M byte page */
ori r8, r8, MI_SVALID /* Make it valid */
mtspr MI_TWC, r8
mtspr MD_TWC, r8
li r8, MI_BOOTINIT|0x2 /* Create RPN for address 0 */
mtspr MI_RPN, r8 /* Store TLB entry */
mtspr MD_RPN, r8
lis r8, MI_Kp@h /* Set the protection mode */
mtspr MI_AP, r8
mtspr MD_AP, r8
/* Now map the higher 8 Meg into the TLBs. For this quick hack,
* we can load the instruction and data TLB registers with the
* same values.
*/
lwz r9,20(r29) /* gd->ram_size */
addis r9,r9,-0x80
mr r8, r9 /* Higher 8 Meg in SDRAM */
ori r8, r8, MI_EVALID /* Mark page valid */
mtspr MI_EPN, r8
mtspr MD_EPN, r8
li r8, MI_PS8MEG /* Set 8M byte page */
ori r8, r8, MI_SVALID /* Make it valid */
mtspr MI_TWC, r8
mtspr MD_TWC, r8
mr r8, r9
ori r8, r8, MI_BOOTINIT|0x2
mtspr MI_RPN, r8 /* Store TLB entry */
mtspr MD_RPN, r8
lis r8, MI_Kp@h /* Set the protection mode */
mtspr MI_AP, r8
mtspr MD_AP, r8
/* Map another 8 MByte at the IMMR to get the processor
* internal registers (among other things).
*/
mfspr r9, 638 /* Get current IMMR */
andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */
mr r8, r9 /* Create vaddr for TLB */
ori r8, r8, MD_EVALID /* Mark it valid */
mtspr MD_EPN, r8
li r8, MD_PS8MEG /* Set 8M byte page */
ori r8, r8, MD_SVALID /* Make it valid */
mtspr MD_TWC, r8
mr r8, r9 /* Create paddr for TLB */
ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
mtspr MD_RPN, r8
/* We now have the lower and higher 8 Meg mapped into TLB entries,
* and the caches ready to work.
*/
mfmsr r0
ori r0,r0,MSR_DR|MSR_IR
mtspr SRR1,r0
mflr r0
mtspr SRR0,r0
SYNC
rfi /* enables MMU */
/*
* void caches_init(void);
*/
.globl caches_init
caches_init:
sync
mfspr r3, IC_CST /* Clear error bits */
mfspr r3, DC_CST
lis r3, IDC_UNALL@h /* Unlock all */
mtspr IC_CST, r3
mtspr DC_CST, r3
lis r3, IDC_INVALL@h /* Invalidate all */
mtspr IC_CST, r3
mtspr DC_CST, r3
lis r3, IDC_ENABLE@h /* Enable all */
mtspr IC_CST, r3
mtspr DC_CST, r3
blr
/*
* void flush_dcache_range(unsigned long start, unsigned long stop);
*/
.global flush_dcache_range
flush_dcache_range:
li r5,CACHE_LINE_SIZE-1
andc r3,r3,r5
subf r4,r3,r4
add r4,r4,r5
srwi. r4,r4,LG_CACHE_LINE_SIZE
beqlr
mtctr r4
1: dcbf 0,r3
addi r3,r3,CACHE_LINE_SIZE
bdnz 1b
sync /* wait for dcbf's to get to ram */
blr
/*
* void disable_interrupts(void);
*/
.global disable_interrupts
disable_interrupts:
mfmsr r0
rlwinm r0,r0,0,17,15
mtmsr r0
blr
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