Commit c262bb74 authored by Tianrui Wei's avatar Tianrui Wei Committed by Leo Yu-Chi Liang
Browse files

board: riscv: add openpiton-riscv64 SoC support



This patch adds openpiton-riscv64 SOC support. In particular, this
board supports a standard bootflow through zsbl->u-boot SPL->
opensbi->u-boot proper->Linux. There are separate defconfigs for
building u-boot SPL and u-boot proper
Signed-off-by: default avatarTianrui Wei <tianrui-wei@outlook.com>
Signed-off-by: default avatarJonathan Balkind <jbalkind@ucsb.edu>
Reviewed-by: default avatarLeo Yu-Chi Liang <ycliang@andestech.com>
parent 1d806f66
......@@ -26,6 +26,9 @@ config TARGET_SIFIVE_UNMATCHED
config TARGET_SIPEED_MAIX
bool "Support Sipeed Maix Board"
config TARGET_OPENPITON_RISCV64
bool "Support RISC-V cores on OpenPiton SoC"
endchoice
config SYS_ICACHE_OFF
......@@ -60,6 +63,7 @@ source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/sifive/unleashed/Kconfig"
source "board/sifive/unmatched/Kconfig"
source "board/openpiton/riscv64/Kconfig"
source "board/sipeed/maix/Kconfig"
# platform-specific options below
......
......@@ -3,6 +3,7 @@
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt.dtb
dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
......
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2021 Tianrui Wei <tianrui-wei@outlook.com> */
/*
* This dts is for a dual core instance of OpenPiton+Ariane built
* to run on a Digilent Genesys 2 FPGA at 66.67MHz. These files
* are automatically generated by the OpenPiton build system and
* this configuration may not be what you need if your configuration
* is different from the below.
*/
/dts-v1/;
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "openpiton,riscv64";
chosen {
stdout-path = "uart0:115200";
};
aliases {
console = &uart0;
serial0 = &uart0;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <520835>;
CPU0: cpu@0 {
clocks = <&clk0>;
u-boot,dm-spl;
device_type = "cpu";
reg = <0>;
compatible = "openhwgroup,cva6", "riscv";
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv39";
tlb-split;
// HLIC - hart local interrupt controller
CPU0_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
CPU1: cpu@1 {
clocks = <&clk0>;
device_type = "cpu";
reg = <1>;
compatible = "openhwgroup,cva6", "riscv";
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv39";
tlb-split;
// HLIC - hart local interrupt controller
CPU1_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
};
clocks {
clk0: osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <66667000>;
};
};
memory@80000000 {
u-boot,dm-spl;
device_type = "memory";
reg = < 0x00000000 0x80000000 0x00000000 0x40000000 >;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "openpiton,chipset", "simple-bus";
ranges;
uart0: uart@fff0c2c000 {
compatible = "ns16550", "openpiton,ns16550";
reg = < 0x000000ff 0xf0c2c000 0x00000000 0x000d4000 >;
interrupt-parent = <&PLIC0>;
interrupts = <1>;
reg-shift = <0>;
// regs are spaced on 8 bit boundary
};
eth: ethernet@fff0d00000 {
compatible = "xlnx,xps-ethernetlite-1.00.a", "openpiton,ethernet";
device_type = "network";
reg = < 0x000000ff 0xf0d00000 0x00000000 0x00100000 >;
interrupt-parent = <&PLIC0>;
interrupts = <2>;
phy-handle = <&phy0>;
xlnx,duplex = <0x1>;
xlnx,include-global-buffers = <0x1>;
xlnx,include-internal-loopback = <0x0>;
xlnx,include-mdio = <0x1>;
xlnx,rx-ping-pong = <0x1>;
xlnx,s-axi-id-width = <0x1>;
xlnx,tx-ping-pong = <0x1>;
xlnx,use-internal = <0x0>;
axi_ethernetlite_0_mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: phy@1 {
compatible = "ethernet-phy-id001C.C915";
device_type = "ethernet-phy";
reg = <1>;
};
};
};
sdhci_0: sdhci@f000000000 {
u-boot,dm-spl;
compatible = "openpiton,piton-mmc", "openpiton,mmc";
reg = < 0x000000f0 0x00000000 0x00000000 0x00300000 >;
};
clint@fff1020000 {
compatible = "sifive,clint0", "openpiton,clint";
interrupts-extended = < &CPU0_intc 3
&CPU0_intc 7
&CPU1_intc 3
&CPU1_intc 7 >;
reg = < 0x000000ff 0xf1020000 0x00000000 0x000c0000 >;
clocks = <&clk0>;
};
PLIC0: plic@fff1100000 {
u-boot,dm-spl;
#interrupt-cells = <1>;
compatible = "sifive,plic-1.0.0", "openpiton,plic";
interrupt-controller;
interrupts-extended = < &CPU0_intc 11
&CPU0_intc 9
&CPU1_intc 11
&CPU1_intc 9 >;
reg = < 0x000000ff 0xf1100000 0x00000000 0x04000000 >;
riscv,max-priority = <7>;
riscv,ndev = <2>;
};
};
};
if TARGET_OPENPITON_RISCV64
config SYS_BOARD
default "riscv64"
config SYS_VENDOR
default "openpiton"
config SYS_CPU
default "generic"
config SYS_CONFIG_NAME
default "openpiton-riscv64"
config SYS_TEXT_BASE
default 0x81000000 if SPL
default 0x80000000 if !RISCV_SMODE
default 0x81000000 if RISCV_SMODE
config SPL_TEXT_BASE
default 0x82000000
config SPL_OPENSBI_LOAD_ADDR
default 0x80000000
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_EARLY_INIT_R
select SUPPORT_SPL
imply CPU_RISCV
imply RISCV_TIMER
imply SPL_SIFIVE_CLINT
imply CMD_CPU
imply SPL_CPU_SUPPORT
imply SPL_SMP
imply SPL_MMC
imply SMP
imply SPL_RISCV_MMODE
endif
Openpiton BOARD
M: Tianrui Wei<tianrui-wei@outlook.com>
S: Maintained
F: board/openpiton/riscv64/
F: include/configs/openpiton-riscv64.h
F: configs/openpiton_riscv64_defconfig
F: configs/openpiton_riscv64_spl_defconfig
F: drivers/mmc/piton_mmc.c
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2021 Tianrui Wei
# Tianrui Wei <tianrui-wei@outlook.com>
obj-y += openpiton-riscv64.o
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2019 SiFive, Inc
* Copyright (c) 2021 Tianrui Wei
*
*
* Authors:
* Pragnesh Patel <pragnesh.patel@sifive.com>
* Tianrui Wei <tianrui-wei@outlook.com>
*/
#include <common.h>
#include <init.h>
#include <configs/openpiton-riscv64.h>
#include <dm.h>
#include <spl.h>
#ifdef CONFIG_SPL
void board_boot_order(u32 *spl_boot_list)
{
u8 i;
u32 boot_devices[] = {
BOOT_DEVICE_MMC1,
};
for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
spl_boot_list[i] = boot_devices[i];
}
#endif
int board_init(void)
{
return 0;
}
CONFIG_RISCV=y
CONFIG_SYS_TEXT_BASE=0x80200000
CONFIG_NR_DRAM_BANKS=1
CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64"
CONFIG_TARGET_OPENPITON_RISCV64=y
CONFIG_ARCH_RV64I=y
CONFIG_CMODEL_MEDANY=y
CONFIG_RISCV_SMODE=y
CONFIG_OF_BOARD_FIXUP=y
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_ENV_VARS_UBOOT_CONFIG=y
# CONFIG_EXPERT is not set
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_SYS_PROMPT="openpiton$ "
# CONFIG_CMD_CPU is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
# CONFIG_CMD_RUN is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_SAVEENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMINFO=y
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNLZ4 is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
# CONFIG_RANDOM_UUID is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_LSBLK=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_READ=y
# CONFIG_CMD_ECHO is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_BLOCK_CACHE is not set
# CONFIG_CMD_DATE is not set
# CONFIG_CMD_SLEEP is not set
CONFIG_CMD_SYSBOOT=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
# CONFIG_DOS_PARTITION is not set
CONFIG_OF_EMBED=y
# CONFIG_NET is not set
CONFIG_CPU=y
CONFIG_MMC=y
# CONFIG_MMC_WRITE is not set
# CONFIG_MMC_HW_PARTITIONING is not set
# CONFIG_MMC_VERBOSE is not set
CONFIG_MMC_PITON=y
CONFIG_RAM=y
# CONFIG_RAM_SIFIVE is not set
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_FS_SQUASHFS=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_SHA1=y
CONFIG_SHA256=y
CONFIG_MD5=y
CONFIG_GETOPT=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SPL_OF_LIBFDT=y
# CONFIG_EFI_LOADER is not set
CONFIG_RISCV=y
CONFIG_SYS_TEXT_BASE=0x80000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000
CONFIG_SPL=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_PAYLOAD=""
CONFIG_DEFAULT_DEVICE_TREE="openpiton-riscv64"
CONFIG_TARGET_OPENPITON_RISCV64=y
CONFIG_NR_CPUS=32
CONFIG_ARCH_RV64I=y
CONFIG_CMODEL_MEDANY=y
CONFIG_RISCV_SMODE=y
# CONFIG_LOCALVERSION_AUTO is not set
CONFIG_ENV_VARS_UBOOT_CONFIG=y
# CONFIG_EXPERT is not set
# CONFIG_LEGACY_IMAGE_FORMAT is not set
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_SEPARATE_BSS=y
# CONFIG_SPL_BANNER_PRINT is not set
CONFIG_SPL_CPU=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_RTC_SUPPORT=y
CONFIG_SYS_PROMPT="openpiton$ "
# CONFIG_CMD_CPU is not set
CONFIG_CMD_BOOTZ=y
# CONFIG_BOOTM_NETBSD is not set
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
# CONFIG_CMD_RUN is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_SAVEENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_MEMINFO=y
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNLZ4 is not set
# CONFIG_CMD_UNZIP is not set
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPT=y
# CONFIG_RANDOM_UUID is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
CONFIG_CMD_LSBLK=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_READ=y
# CONFIG_CMD_ECHO is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_BLOCK_CACHE is not set
# CONFIG_CMD_DATE is not set
# CONFIG_CMD_SLEEP is not set
CONFIG_CMD_SYSBOOT=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
# CONFIG_DOS_PARTITION is not set
# CONFIG_SPL_PARTITION_UUIDS is not set
# CONFIG_NET is not set
CONFIG_CPU=y
CONFIG_MMC=y
# CONFIG_MMC_WRITE is not set
# CONFIG_MMC_HW_PARTITIONING is not set
# CONFIG_MMC_VERBOSE is not set
CONFIG_MMC_PITON=y
CONFIG_RAM=y
# CONFIG_RAM_SIFIVE is not set
CONFIG_DM_RTC=y
CONFIG_SYS_NS16550=y
CONFIG_FS_SQUASHFS=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPL_TINY_MEMSET=y
CONFIG_SHA1=y
CONFIG_SHA256=y
CONFIG_MD5=y
CONFIG_GETOPT=y
CONFIG_OF_LIBFDT_OVERLAY=y
# CONFIG_EFI_LOADER is not set
......@@ -18,6 +18,7 @@ Board-specific doc
intel/index
kontron/index
microchip/index
openpiton/index
rockchip/index
sifive/index
sipeed/index
......
.. SPDX-License-Identifier: GPL-2.0+
OpenPiton
=========
.. toctree::
:maxdepth: 2
riscv64
.. SPDX-License-Identifier: GPL-2.0+
Openpiton RISC-V SoC
====================
OpenPiton RISC-V SoC
--------------------
OpenPiton is an open source, manycore processor and research platform. It is a
tiled manycore framework scalable from one to 1/2 billion cores. It supports a
number of ISAs including RISC-V with its P-Mesh cache coherence protocol and
networks on chip. It is highly configurable in both core and uncore components.
OpenPiton has been verified in both ASIC and multiple Xilinx FPGA prototypes
running full-stack Debian linux.
RISC-V Standard Bootflow
-------------------------
Currently, OpenPiton implements RISC-V standard bootflow in the following steps
mover.S -> u-boot-spl -> opensbi -> u-boot -> Linux
This board supports S-mode u-boot as well as M-mode SPL
Building OpenPition
---------------------
If you'd like to build OpenPiton, please go to OpenPiton github repo
(at https://github.com/PrincetonUniversity/openpiton) to build from the latest
changes
Building Images
---------------------------
SPL
---
1. Add the RISC-V toolchain to your PATH.
2. Setup ARCH & cross compilation environment variable:
.. code-block:: none
export CROSS_COMPILE=<riscv64 toolchain prefix>
export ARCH=riscv
3. make openpiton_riscv64_spl_defconfig
4. make
U-Boot
------
1. Add the RISC-V toolchain to your PATH.
2. Setup ARCH & cross compilation environment variable:
.. code-block:: none
export CROSS_COMPILE=<riscv64 toolchain prefix>
export ARCH=riscv
3. make openpiton_riscv64_defconfig
4. make
opensbi
-------
1. Add the RISC-V toolchain to your PATH.
2. Setup ARCH & cross compilation environment variable:
.. code-block:: none
export CROSS_COMPILE=<riscv64 toolchain prefix>
export ARCH=riscv
3. Go to OpenSBI directory
4. make PLATFORM=fpga/openpiton FW_PAYLOAD_PATH=<path to u-boot-nodtb.bin>
Using fw_payload.bin with linux
-------------------------------
Put the generated fw_payload.bin into the /boot directory on the root filesystem,
plug in the SD card, then flash the bitstream. Linux will boot automatically.
Booting
-------
Once you plugin the sdcard and power up, you should see the U-Boot prompt.
Sample Dual-core Debian boot log from OpenPiton
-----------------------------------------------
.. code-block:: none
Trying to boot from MMC1
OpenSBI v0.9-5-gd06cb61
____ _____ ____ _____
/ __ \ / ____| _ \_ _|
| | | |_ __ ___ _ __ | (___ | |_) || |
| | | | '_ \ / _ \ '_ \ \___ \| _ < | |
| |__| | |_) | __/ | | |____) | |_) || |_
\____/| .__/ \___|_| |_|_____/|____/_____|
| |
|_|
Platform Name : OPENPITON RISC-V
Platform Features : timer,mfdeleg
Platform HART Count : 3
Firmware Base : 0x80000000
Firmware Size : 104 KB
Runtime SBI Version : 0.2
Domain0 Name : root
Domain0 Boot HART : 0
Domain0 HARTs : 0*,1*,2*
Domain0 Region00 : 0x0000000080000000-0x000000008001ffff ()
Domain0 Region01 : 0x0000000000000000-0xffffffffffffffff (R,W,X)
Domain0 Next Address : 0x0000000080200000
Domain0 Next Arg1 : 0x0000000082200000
Domain0 Next Mode : S-mode
Domain0 SysReset : yes
Boot HART ID : 0
Boot HART Domain : root
Boot HART ISA : rv64imafdcsu
Boot HART Features : scounteren,mcounteren
Boot HART PMP Count : 0
Boot HART PMP Granularity : 0
Boot HART PMP Address Bits: 0
Boot HART MHPM Count : 0
Boot HART MHPM Count : 0
Boot HART MIDELEG : 0x0000000000000222
Boot HART MEDELEG : 0x000000000000b109
U-Boot 2021.01+ (Jun 12 2021 - 10:31:34 +0800)
DRAM: 1 GiB
MMC: sdhci@f000000000: 0 (eMMC)
In: uart@fff0c2c000
Out: uart@fff0c2c000
Err: uart@fff0c2c000
Hit any key to stop autoboot: 0
6492992 bytes read in 5310 ms (1.2 MiB/s)
## Flattened Device Tree blob at 86000000
Booting using the fdt blob at 0x86000000
Loading Device Tree to 00000000bfffa000, end 00000000bffff007 ... OK
Starting kernel ...
[ 0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000
[ 0.000000] Linux version 5.6.0-rc4-gb9d34f7e294d-dirty
[ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '')
[ 0.000000] printk: bootconsole [sbi0] enabled
[ 0.000000] Zone ranges:
[ 0.000000] DMA32 [mem 0x0000000080200000-0x00000000bfffffff]
[ 0.000000] Normal empty
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000080200000-0x00000000bfffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x00000000bfffffff]
[ 0.000000] On node 0 totalpages: 261632
[ 0.000000] DMA32 zone: 4088 pages used for memmap
[ 0.000000] DMA32 zone: 0 pages reserved
[ 0.000000] DMA32 zone: 261632 pages, LIFO batch:63
[ 0.000000] software IO TLB: mapped [mem 0xbaffa000-0xbeffa000] (64MB)
[ 0.000000] SBI specification v0.2 detected
[ 0.000000] SBI implementation ID=0x1 Version=0x9
[ 0.000000] SBI v0.2 TIME extension detected
[ 0.000000] SBI v0.2 IPI extension detected
[ 0.000000] SBI v0.2 RFENCE extension detected
[ 0.000000] SBI v0.2 HSM extension detected
[ 0.000000] elf_hwcap is 0x112d
[ 0.000000] percpu: Embedded 16 pages/cpu s25368 r8192 d31976 u65536
[ 0.000000] pcpu-alloc: s25368 r8192 d31976 u65536 alloc=16*4096
[ 0.000000] pcpu-alloc: [0] 0
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 257544
[ 0.000000] Kernel command line: earlycon=sbi root=/dev/piton_sd1
[ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
[ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
[ 0.000000] Sorting __ex_table...
[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
[ 0.000000] Memory: 956252K/1046528K available (4357K kernel code, 286K rwdata, 1200K rodata, 168K init, 311K bss, 90276K re)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[ 0.000000] rcu: Hierarchical RCU implementation.
[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=1.
[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
[ 0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
[ 0.000000] plic: mapped 2 interrupts with 1 handlers for 2 contexts.
[ 0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [0]
[ 0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1ec037a6a, max_idle_ns: 7052723236599 ns
[ 0.000138] sched_clock: 64 bits at 520kHz, resolution 1919ns, wraps every 4398046510738ns
[ 0.009429] printk: console [hvc0] enabled
[ 0.009429] printk: console [hvc0] enabled