Commit c552debb authored by Green Wan's avatar Green Wan Committed by Leo Yu-Chi Liang
Browse files

riscv: cpu: fu740: clear feature disable CSR

Clear feature disable CSR to turn on all features of hart. The detail
is specified at section, 'SiFive Feature Disable CSR', in user manual

https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf

Signed-off-by: default avatarGreen Wan <green.wan@sifive.com>
Reviewed-by: Sean Anderson's avatarSean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng's avatarBin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen's avatarRick Chen <rick@andestech.com>
parent 70415e1e
......@@ -6,6 +6,9 @@
#include <dm.h>
#include <log.h>
#include <asm/csr.h>
#define CSR_U74_FEATURE_DISABLE 0x7c1
int spl_soc_init(void)
{
......@@ -21,3 +24,15 @@ int spl_soc_init(void)
return 0;
}
void harts_early_init(void)
{
/*
* Feature Disable CSR
*
* Clear feature disable CSR to '0' to turn on all features for
* each core. This operation must be in M-mode.
*/
if (CONFIG_IS_ENABLED(RISCV_MMODE))
csr_write(CSR_U74_FEATURE_DISABLE, 0);
}
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