Commit f6127db8 authored by Tom Rini's avatar Tom Rini

Merge https://source.denx.de/u-boot/custodians/u-boot-riscv

- Watchdog, Unleashed and Icicle improvements
parents 8246654e e7bb113c
Pipeline #7094 passed with stages
in 110 minutes and 45 seconds
......@@ -17,8 +17,8 @@ config TARGET_MICROCHIP_ICICLE
config TARGET_QEMU_VIRT
bool "Support QEMU Virt Board"
config TARGET_SIFIVE_FU540
bool "Support SiFive FU540 Board"
config TARGET_SIFIVE_UNLEASHED
bool "Support SiFive Unleashed Board"
config TARGET_SIPEED_MAIX
bool "Support Sipeed Maix Board"
......@@ -55,7 +55,7 @@ config SPL_SYS_DCACHE_OFF
source "board/AndesTech/ax25-ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/sifive/fu540/Kconfig"
source "board/sifive/unleashed/Kconfig"
source "board/sipeed/maix/Kconfig"
# platform-specific options below
......@@ -271,4 +271,82 @@ config STACK_SIZE_SHIFT
config OF_BOARD_FIXUP
default y if OF_SEPARATE && RISCV_SMODE
config USE_ARCH_MEMCPY
bool "Use an assembly optimized implementation of memcpy"
default y
help
Enable the generation of an optimized version of memcpy.
Such an implementation may be faster under some conditions
but may increase the binary size.
config SPL_USE_ARCH_MEMCPY
bool "Use an assembly optimized implementation of memcpy for SPL"
default y if USE_ARCH_MEMCPY
depends on SPL
help
Enable the generation of an optimized version of memcpy.
Such an implementation may be faster under some conditions
but may increase the binary size.
config TPL_USE_ARCH_MEMCPY
bool "Use an assembly optimized implementation of memcpy for TPL"
default y if USE_ARCH_MEMCPY
depends on TPL
help
Enable the generation of an optimized version of memcpy.
Such an implementation may be faster under some conditions
but may increase the binary size.
config USE_ARCH_MEMMOVE
bool "Use an assembly optimized implementation of memmove"
default y
help
Enable the generation of an optimized version of memmove.
Such an implementation may be faster under some conditions
but may increase the binary size.
config SPL_USE_ARCH_MEMMOVE
bool "Use an assembly optimized implementation of memmove for SPL"
default y if USE_ARCH_MEMCPY
depends on SPL
help
Enable the generation of an optimized version of memmove.
Such an implementation may be faster under some conditions
but may increase the binary size.
config TPL_USE_ARCH_MEMMOVE
bool "Use an assembly optimized implementation of memmove for TPL"
default y if USE_ARCH_MEMCPY
depends on TPL
help
Enable the generation of an optimized version of memmove.
Such an implementation may be faster under some conditions
but may increase the binary size.
config USE_ARCH_MEMSET
bool "Use an assembly optimized implementation of memset"
default y
help
Enable the generation of an optimized version of memset.
Such an implementation may be faster under some conditions
but may increase the binary size.
config SPL_USE_ARCH_MEMSET
bool "Use an assembly optimized implementation of memset for SPL"
default y if USE_ARCH_MEMSET
depends on SPL
help
Enable the generation of an optimized version of memset.
Such an implementation may be faster under some conditions
but may increase the binary size.
config TPL_USE_ARCH_MEMSET
bool "Use an assembly optimized implementation of memset for TPL"
default y if USE_ARCH_MEMSET
depends on TPL
help
Enable the generation of an optimized version of memset.
Such an implementation may be faster under some conditions
but may increase the binary size.
endmenu
# SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
......
......@@ -439,7 +439,6 @@
interrupts = <21>;
clocks = <&sysclk K210_CLK_WDT0>;
resets = <&sysrst K210_RST_WDT0>;
status = "disabled";
};
wdt1: watchdog@50410000 {
......
......@@ -232,7 +232,6 @@
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <90>;
clock-frequency = <150000000>;
clocks = <&clkcfg CLK_MMUART0>;
status = "okay";
};
......@@ -294,7 +293,6 @@
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <91>;
clock-frequency = <150000000>;
clocks = <&clkcfg CLK_MMUART1>;
status = "okay";
};
......@@ -305,7 +303,6 @@
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <92>;
clock-frequency = <150000000>;
clocks = <&clkcfg CLK_MMUART2>;
status = "okay";
};
......@@ -316,7 +313,6 @@
reg-shift = <2>;
interrupt-parent = <&plic>;
interrupts = <93>;
clock-frequency = <150000000>;
clocks = <&clkcfg CLK_MMUART3>;
status = "okay";
};
......
......@@ -19,31 +19,25 @@
#undef __HAVE_ARCH_STRRCHR
#undef __HAVE_ARCH_STRCHR
#undef __HAVE_ARCH_MEMCPY
#undef __HAVE_ARCH_MEMMOVE
#undef __HAVE_ARCH_MEMCHR
#undef __HAVE_ARCH_MEMZERO
#undef __HAVE_ARCH_MEMSET
#ifdef CONFIG_MARCO_MEMSET
#define memset(_p, _v, _n) \
(typeof(_p) (p) = (_p); \
typeof(_v) (v) = (_v); \
typeof(_n) (n) = (_n); \
{ \
if ((n) != 0) { \
if (__builtin_constant_p((v)) && (v) == 0) \
__memzero((p), (n)); \
else \
memset((p), (v), (n)); \
} \
(p); \
})
#undef __HAVE_ARCH_MEMCPY
#if CONFIG_IS_ENABLED(USE_ARCH_MEMCPY)
#define __HAVE_ARCH_MEMCPY
#endif
extern void *memcpy(void *, const void *, __kernel_size_t);
#undef __HAVE_ARCH_MEMMOVE
#if CONFIG_IS_ENABLED(USE_ARCH_MEMMOVE)
#define __HAVE_ARCH_MEMMOVE
#endif
extern void *memmove(void *, const void *, __kernel_size_t);
#define memzero(_p, _n) \
(typeof(_p) (p) = (_p); \
typeof(_n) (n) = (_n); \
{ if ((n) != 0) __memzero((p), (n)); (p); })
#undef __HAVE_ARCH_MEMZERO
#if CONFIG_IS_ENABLED(USE_ARCH_MEMSET)
#define __HAVE_ARCH_MEMSET
#endif
extern void *memset(void *, int, __kernel_size_t);
#endif /* __ASM_RISCV_STRING_H */
......@@ -36,3 +36,7 @@ CFLAGS_REMOVE_$(EFI_RELOC) := $(CFLAGS_NON_EFI)
extra-$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE) += $(EFI_CRT0) $(EFI_RELOC)
extra-$(CONFIG_CMD_BOOTEFI_SELFTEST) += $(EFI_CRT0) $(EFI_RELOC)
extra-$(CONFIG_EFI) += $(EFI_CRT0) $(EFI_RELOC)
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMMOVE) += memmove.o
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2013 Regents of the University of California
*/
#include <linux/linkage.h>
#include <asm/asm.h>
/* void *memcpy(void *, const void *, size_t) */
ENTRY(__memcpy)
WEAK(memcpy)
move t6, a0 /* Preserve return value */
/* Defer to byte-oriented copy for small sizes */
sltiu a3, a2, 128
bnez a3, 4f
/* Use word-oriented copy only if low-order bits match */
andi a3, t6, SZREG-1
andi a4, a1, SZREG-1
bne a3, a4, 4f
beqz a3, 2f /* Skip if already aligned */
/*
* Round to nearest double word-aligned address
* greater than or equal to start address
*/
andi a3, a1, ~(SZREG-1)
addi a3, a3, SZREG
/* Handle initial misalignment */
sub a4, a3, a1
1:
lb a5, 0(a1)
addi a1, a1, 1
sb a5, 0(t6)
addi t6, t6, 1
bltu a1, a3, 1b
sub a2, a2, a4 /* Update count */
2:
andi a4, a2, ~((16*SZREG)-1)
beqz a4, 4f
add a3, a1, a4
3:
REG_L a4, 0(a1)
REG_L a5, SZREG(a1)
REG_L a6, 2*SZREG(a1)
REG_L a7, 3*SZREG(a1)
REG_L t0, 4*SZREG(a1)
REG_L t1, 5*SZREG(a1)
REG_L t2, 6*SZREG(a1)
REG_L t3, 7*SZREG(a1)
REG_L t4, 8*SZREG(a1)
REG_L t5, 9*SZREG(a1)
REG_S a4, 0(t6)
REG_S a5, SZREG(t6)
REG_S a6, 2*SZREG(t6)
REG_S a7, 3*SZREG(t6)
REG_S t0, 4*SZREG(t6)
REG_S t1, 5*SZREG(t6)
REG_S t2, 6*SZREG(t6)
REG_S t3, 7*SZREG(t6)
REG_S t4, 8*SZREG(t6)
REG_S t5, 9*SZREG(t6)
REG_L a4, 10*SZREG(a1)
REG_L a5, 11*SZREG(a1)
REG_L a6, 12*SZREG(a1)
REG_L a7, 13*SZREG(a1)
REG_L t0, 14*SZREG(a1)
REG_L t1, 15*SZREG(a1)
addi a1, a1, 16*SZREG
REG_S a4, 10*SZREG(t6)
REG_S a5, 11*SZREG(t6)
REG_S a6, 12*SZREG(t6)
REG_S a7, 13*SZREG(t6)
REG_S t0, 14*SZREG(t6)
REG_S t1, 15*SZREG(t6)
addi t6, t6, 16*SZREG
bltu a1, a3, 3b
andi a2, a2, (16*SZREG)-1 /* Update count */
4:
/* Handle trailing misalignment */
beqz a2, 6f
add a3, a1, a2
/* Use word-oriented copy if co-aligned to word boundary */
or a5, a1, t6
or a5, a5, a3
andi a5, a5, 3
bnez a5, 5f
7:
lw a4, 0(a1)
addi a1, a1, 4
sw a4, 0(t6)
addi t6, t6, 4
bltu a1, a3, 7b
ret
5:
lb a4, 0(a1)
addi a1, a1, 1
sb a4, 0(t6)
addi t6, t6, 1
bltu a1, a3, 5b
6:
ret
END(__memcpy)
/* SPDX-License-Identifier: GPL-2.0 */
#include <linux/linkage.h>
#include <asm/asm.h>
ENTRY(__memmove)
WEAK(memmove)
move t0, a0
move t1, a1
beq a0, a1, exit_memcpy
beqz a2, exit_memcpy
srli t2, a2, 0x2
slt t3, a0, a1
beqz t3, do_reverse
andi a2, a2, 0x3
li t4, 1
beqz t2, byte_copy
word_copy:
lw t3, 0(a1)
addi t2, t2, -1
addi a1, a1, 4
sw t3, 0(a0)
addi a0, a0, 4
bnez t2, word_copy
beqz a2, exit_memcpy
j byte_copy
do_reverse:
add a0, a0, a2
add a1, a1, a2
andi a2, a2, 0x3
li t4, -1
beqz t2, reverse_byte_copy
reverse_word_copy:
addi a1, a1, -4
addi t2, t2, -1
lw t3, 0(a1)
addi a0, a0, -4
sw t3, 0(a0)
bnez t2, reverse_word_copy
beqz a2, exit_memcpy
reverse_byte_copy:
addi a0, a0, -1
addi a1, a1, -1
byte_copy:
lb t3, 0(a1)
addi a2, a2, -1
sb t3, 0(a0)
add a1, a1, t4
add a0, a0, t4
bnez a2, byte_copy
exit_memcpy:
move a0, t0
move a1, t1
ret
END(__memmove)
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2013 Regents of the University of California
*/
#include <linux/linkage.h>
#include <asm/asm.h>
/* void *memset(void *, int, size_t) */
ENTRY(__memset)
WEAK(memset)
move t0, a0 /* Preserve return value */
/* Defer to byte-oriented fill for small sizes */
sltiu a3, a2, 16
bnez a3, 4f
/*
* Round to nearest XLEN-aligned address
* greater than or equal to start address
*/
addi a3, t0, SZREG-1
andi a3, a3, ~(SZREG-1)
beq a3, t0, 2f /* Skip if already aligned */
/* Handle initial misalignment */
sub a4, a3, t0
1:
sb a1, 0(t0)
addi t0, t0, 1
bltu t0, a3, 1b
sub a2, a2, a4 /* Update count */
2: /* Duff's device with 32 XLEN stores per iteration */
/* Broadcast value into all bytes */
andi a1, a1, 0xff
slli a3, a1, 8
or a1, a3, a1
slli a3, a1, 16
or a1, a3, a1
#ifdef CONFIG_64BIT
slli a3, a1, 32
or a1, a3, a1
#endif
/* Calculate end address */
andi a4, a2, ~(SZREG-1)
add a3, t0, a4
andi a4, a4, 31*SZREG /* Calculate remainder */
beqz a4, 3f /* Shortcut if no remainder */
neg a4, a4
addi a4, a4, 32*SZREG /* Calculate initial offset */
/* Adjust start address with offset */
sub t0, t0, a4
/* Jump into loop body */
/* Assumes 32-bit instruction lengths */
la a5, 3f
#ifdef CONFIG_64BIT
srli a4, a4, 1
#endif
add a5, a5, a4
jr a5
3:
REG_S a1, 0(t0)
REG_S a1, SZREG(t0)
REG_S a1, 2*SZREG(t0)
REG_S a1, 3*SZREG(t0)
REG_S a1, 4*SZREG(t0)
REG_S a1, 5*SZREG(t0)
REG_S a1, 6*SZREG(t0)
REG_S a1, 7*SZREG(t0)
REG_S a1, 8*SZREG(t0)
REG_S a1, 9*SZREG(t0)
REG_S a1, 10*SZREG(t0)
REG_S a1, 11*SZREG(t0)
REG_S a1, 12*SZREG(t0)
REG_S a1, 13*SZREG(t0)
REG_S a1, 14*SZREG(t0)
REG_S a1, 15*SZREG(t0)
REG_S a1, 16*SZREG(t0)
REG_S a1, 17*SZREG(t0)
REG_S a1, 18*SZREG(t0)
REG_S a1, 19*SZREG(t0)
REG_S a1, 20*SZREG(t0)
REG_S a1, 21*SZREG(t0)
REG_S a1, 22*SZREG(t0)
REG_S a1, 23*SZREG(t0)
REG_S a1, 24*SZREG(t0)
REG_S a1, 25*SZREG(t0)
REG_S a1, 26*SZREG(t0)
REG_S a1, 27*SZREG(t0)
REG_S a1, 28*SZREG(t0)
REG_S a1, 29*SZREG(t0)
REG_S a1, 30*SZREG(t0)
REG_S a1, 31*SZREG(t0)
addi t0, t0, 32*SZREG
bltu t0, a3, 3b
andi a2, a2, SZREG-1 /* Update count */
4:
/* Handle trailing misalignment */
beqz a2, 6f
add a3, t0, a2
5:
sb a1, 0(t0)
addi t0, t0, 1
bltu t0, a3, 5b
6:
ret
END(__memset)
......@@ -54,12 +54,8 @@ ENTRY(longjmp)
LOAD_IDX(sp, 13)
/* Move the return value in place, but return 1 if passed 0. */
beq a1, zero, longjmp_1
mv a0, a1
ret
longjmp_1:
li a0, 1
seqz a0, a1
add a0, a0, a1
ret
ENDPROC(longjmp)
.popsection
if TARGET_SIFIVE_FU540
if TARGET_SIFIVE_UNLEASHED
config SYS_BOARD
default "fu540"
default "unleashed"
config SYS_VENDOR
default "sifive"
......@@ -10,7 +10,7 @@ config SYS_CPU
default "fu540"
config SYS_CONFIG_NAME
default "sifive-fu540"
default "sifive-unleashed"
config SYS_TEXT_BASE
default 0x80200000 if SPL
......
SiFive FU540 BOARD
SiFive HiFive Unleashed BOARD
M: Paul Walmsley <paul.walmsley@sifive.com>
M: Palmer Dabbelt <palmer@dabbelt.com>
M: Anup Patel <anup.patel@wdc.com>
M: Atish Patra <atish.patra@wdc.com>
S: Maintained
F: board/sifive/fu540/
F: doc/board/sifive/fu540.rst
F: include/configs/sifive-fu540.h
F: configs/sifive_fu540_defconfig
F: board/sifive/unleashed/
F: doc/board/sifive/unleashed.rst
F: include/configs/sifive-unleashed.h
F: configs/sifive_unleashed_defconfig
......@@ -2,7 +2,7 @@
#
# Copyright (c) 2019 Western Digital Corporation or its affiliates.
obj-y += fu540.o
obj-y += unleashed.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
......
......@@ -69,4 +69,6 @@ config BOARD_SPECIFIC_OPTIONS
imply EFI_PARTITION
imply CMD_PART
imply CMD_FS_GENERIC
imply WDT
imply DESIGNWARE_WATCHDOG
endif
......@@ -330,7 +330,8 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
ARCH_MX6 || ARCH_MX7 || \
ARCH_ROCKCHIP || ARCH_MVEBU || ARCH_SOCFPGA || \
ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \
OMAP44XX || OMAP54XX || AM33XX || AM43XX || TARGET_SIFIVE_FU540
OMAP44XX || OMAP54XX || AM33XX || AM43XX || \
TARGET_SIFIVE_UNLEASHED
help
Use sector number for specifying U-Boot location on MMC/SD in
raw mode.
......@@ -347,7 +348,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
default 0x300 if ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || OMAP44XX || \
OMAP54XX || AM33XX || AM43XX || ARCH_K3
default 0x4000 if ARCH_ROCKCHIP
default 0x822 if TARGET_SIFIVE_FU540
default 0x822 if TARGET_SIFIVE_UNLEASHED
help
Address on the MMC to load U-Boot from, when the MMC is being used
in raw mode. Units: MMC sectors (1 sector = 512 bytes).
......
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_ENV_SIZE=0x2000
CONFIG_DEFAULT_DEVICE_TREE="microchip-mpfs-icicle-kit"
CONFIG_TARGET_MICROCHIP_ICICLE=y
......
......@@ -8,7 +8,7 @@ CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00"
CONFIG_TARGET_SIFIVE_FU540=y
CONFIG_TARGET_SIFIVE_UNLEASHED=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_DISTRO_DEFAULTS=y
......
CONFIG_RISCV=y
CONFIG_SYS_TEXT_BASE=0x80020000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0xfff000
CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_TARGET_SIPEED_MAIX=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_STACK_SIZE=0x100000
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run k210_bootcmd"