1. 17 Jun, 2021 5 commits
    • Sean Anderson's avatar
      clk: k210: Re-add support for setting rate · 29e3067d
      Sean Anderson authored
      
      
      This adds support for setting clock rates, which was left out of the
      initial CCF expunging. There are several tricky bits here, mostly related
      to the PLLS:
      
      * The PLL's bypass is broken. If the PLL is reconfigured, any child clocks
        will be stopped.
      * PLL0 is the parent of ACLK which is the CPU and SRAM's clock. To prevent
        stopping the CPU while we configure PLL0's rate, ACLK is reparented
        to IN0 while PLL0 is disabled.
      * PLL1 is the parent of the AISRAM clock. This clock cannot be reparented,
        so we instead just disallow changing PLL1's rate after relocation (when
        we are using the AISRAM).
      Signed-off-by: Sean Anderson's avatarSean Anderson <seanga2@gmail.com>
      Reviewed-by: default avatarLeo Yu-Chi Liang <ycliang@andestech.com>
      29e3067d
    • Sean Anderson's avatar
      clk: k210: Implement soc_clk_dump · 612a8334
      Sean Anderson authored
      
      
      Since we are no longer using CCF we cannot use the default soc_clk_dump.
      Instead, implement our own.
      Signed-off-by: Sean Anderson's avatarSean Anderson <seanga2@gmail.com>
      Reviewed-by: default avatarLeo Yu-Chi Liang <ycliang@andestech.com>
      612a8334
    • Sean Anderson's avatar
      clk: k210: Move pll into the rest of the driver · af9f9974
      Sean Anderson authored
      
      
      Now that there no separate PLL driver, we can no longer make the PLL
      functions static. By moving the PLL driver in with the rest of the clock
      code, we can make these functions static again. We still keep the pll
      header for unit testing, but it is pretty reduced.
      Signed-off-by: Sean Anderson's avatarSean Anderson <seanga2@gmail.com>
      Reviewed-by: default avatarLeo Yu-Chi Liang <ycliang@andestech.com>
      af9f9974
    • Sean Anderson's avatar
      clk: k210: Rewrite to remove CCF · 609bd60b
      Sean Anderson authored
      
      
      This is effectively a complete rewrite to remove all dependency on CCF.
      The code is now smaller, and so is the binary. It also takes up less memory
      at runtime (since we don't have to create 40 udevices). In general, I am
      much happier with this driver as much of the complexity and late binding
      has been removed.
      
      The k210_*_params structs which were previously used to initialize CCF
      clocks are now used as the complete configuration. Since we can write our
      own division logic, we can now do away with several "half" clocks which
      only existed to provide constant factors of two.
      
      The clock IDs have been renumbered to remove unused clocks. This may not be
      the last time they are renumbered, since we have diverged with Linux. There
      are also still a few clocks left out which may need to be added back in.
      
      In general, I have tried to leave out behavioral changes. However, there is
      a small bugfix regarding ACLK. According to the technical reference manual,
      its mux comes *after* its divider (which is present only for PLL0). This
      would have required yet another intermediate clock to fix with CCF, but
      with the new driver it is just 2 lines of code :)
      Signed-off-by: Sean Anderson's avatarSean Anderson <seanga2@gmail.com>
      Reviewed-by: default avatarLeo Yu-Chi Liang <ycliang@andestech.com>
      609bd60b
    • Sean Anderson's avatar
      clk: Allow force setting clock defaults before relocation · 6e33eba5
      Sean Anderson authored
      Since 291da96b
      
       ("clk: Allow clock defaults to be set during re-reloc
      state for SPL only") it has been impossible to set clock defaults before
      relocation. This is annoying on boards without SPL, since there is no way
      to set clock defaults before U-Boot proper. In particular, the aisram rate
      must be changed before relocation on the K210, since U-Boot will hang if we
      try and change the rate while we are using aisram.
      
      To get around this, extend the stage parameter to allow force setting
      defaults, even if they would be otherwise postponed for later. A device
      tree property was decided against because of the concerns in the original
      commit thread about the overhead of repeatedly parsing the device tree.
      Signed-off-by: Sean Anderson's avatarSean Anderson <seanga2@gmail.com>
      Reviewed-by: Simon Glass's avatarSimon Glass <sjg@chromium.org>
      6e33eba5
  2. 13 Jun, 2021 1 commit
  3. 11 Jun, 2021 33 commits
  4. 09 Jun, 2021 1 commit