1. 23 Jan, 2010 1 commit
  2. 28 Jul, 2009 1 commit
  3. 24 Jul, 2009 2 commits
  4. 18 Jul, 2009 1 commit
  5. 16 Apr, 2009 1 commit
  6. 12 Feb, 2009 1 commit
    • Adam Graham's avatar
      ppc4xx: Autocalibration can set RDCC to over aggressive value. · c645012a
      Adam Graham authored and Stefan Roese's avatar Stefan Roese committed
      
      
      The criteria of the AMCC SDRAM Controller DDR autocalibration
      U-Boot code is to pick the largest passing write/read/compare
      window that also has the smallest SDRAM_RDCC.[RDSS] Read Sample
      Cycle Select value.
      
      On some Kilauea boards the DDR autocalibration algorithm can
      find a large passing write/read/compare window with a small
      SDRAM_RDCC.[RDSS] aggressive value of Read Sample Cycle Select
      value "T1 Sample".
      
      This SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of
      "T1 Sample" proves to be to aggressive when later on U-Boot
      relocates into DDR memory and executes.
      
      The memory traces on the Kilauea board are short so on some
      Kilauea boards the SDRAM_RDCC.[RDSS] Read Sample Cycle Select
      value of "T1 Sample" shows up as a potentially valid value for
      the DDR autocalibratiion algorithm.
      
      The fix is to define a weak default function which provides
      the minimum SDRAM_RDCC.[RDSS] Read Sample Cycle Select value
      to accept for DDR autocalibration.  The default will be the
      "T2 Sample" value.  A board developer who has a well defined
      board and chooses to be more aggressive can always provide
      their own board specific string function with the more
      aggressive "T1 Sample" value or stick with the default
      minimum SDRAM_RDCC.[RDSS] value of "T2".
      
      Also put in a autocalibration loop fix for case where current
      write/read/compare passing window size is the same as a prior
      window size, then in this case choose the write/read/compare
      result that has the associated smallest RDCC T-Sample value.
      Signed-off-by: default avatarAdam Graham <agraham@amcc.com>
      Signed-off-by: Stefan Roese's avatarStefan Roese <sr@denx.de>
      c645012a
  7. 23 Jan, 2009 1 commit
  8. 24 Oct, 2008 1 commit
    • Stefan Roese's avatar
      ppc4xx: Disable DDR2 autocalibration on Kilauea for now · 485c00a5
      Stefan Roese authored
      
      
      Since the new autocalibration still has some problems on some Kilauea
      boards with 200MHz DDR2 frequency we disable the autocalibration and
      use the hardcoded values as done before. This seems to work reliably
      on all known DDR2 frequencies.
      
      After the autocalibration issue is fixed we will enable it again.
      Signed-off-by: Stefan Roese's avatarStefan Roese <sr@denx.de>
      485c00a5
  9. 18 Oct, 2008 1 commit
  10. 10 Sep, 2008 3 commits
  11. 05 Sep, 2008 1 commit
  12. 12 Aug, 2008 1 commit
  13. 11 Jul, 2008 2 commits
    • Grant Erickson's avatar
      ppc4xx: Add MII mode support to the EMAC RGMII Bridge · 1740c1bf
      Grant Erickson authored and Stefan Roese's avatar Stefan Roese committed
      
      
      This patch adds support for placing the RGMII bridge on the
      PPC405EX(r) into MII/GMII mode and allows a board-specific
      configuration to specify the bridge mode at compile-time.
      Signed-off-by: default avatarGrant Erickson <gerickson@nuovations.com>
      Signed-off-by: Stefan Roese's avatarStefan Roese <sr@denx.de>
      1740c1bf
    • Grant Erickson's avatar
      ppc4xx: Add Mnemonics for AMCC/IBM DDR2 SDRAM Controller · 2e205084
      Grant Erickson authored and Stefan Roese's avatar Stefan Roese committed
      
      
      This patch completes the preprocessor mneomics for the IBM DDR2 SDRAM
      controller registers (MODT and INITPLR) used by the
      PowerPC405EX(r). The MMODE and MEMODE registers are unified with their
      peer values used for the INITPLR MR and EMR registers,
      respectively. Finally, a spelling typo is correct (MANUEL to MANUAL).
      
      With these mnemonics in place, the CFG_SDRAM0_* magic numbers for
      Kilauea are replaced by equivalent mnemonics to make it easier to
      compare and contrast other 405EX(r)-based boards (e.g. during board
      bring-up).
      
      Finally, unified the SDRAM controller register dump routine such that
      it can be used across all processor variants that utilize the IBM DDR2
      SDRAM controller core. It produces output of the form:
      
      	PPC4xx IBM DDR2 Register Dump:
      		...
      	        SDRAM_MB0CF[40] = 0x00006701
      		...
      
      which is '<mnemonic>[<DCR #>] = <value>'. The DCR number is included
      since it is not uncommon that the DCR values in header files get mixed
      up and it helps to validate, at a glance, they match what is printed
      in the user manual.
      
      Tested on:
        AMCC Kilauea/Haleakala:
        - NFS Linux Boot: PASSED
        - NAND Linux Boot: PASSED
      Signed-off-by: default avatarGrant Erickson <gerickson@nuovations.com>
      Signed-off-by: Stefan Roese's avatarStefan Roese <sr@denx.de>
      2e205084
  14. 06 Jun, 2008 1 commit
    • Stefan Roese's avatar
      ppc4xx: Unify AMCC's board config files (part 2/3) · 490f2040
      Stefan Roese authored
      
      
      This patch series unifies the AMCC eval board ports by introducing
      a common include header for all AMCC eval boards:
      
      include/configs/amcc-common.h
      
      This header now includes all common configuration options/defines which
      are removed from the board specific headers.
      
      The reason for this is ease of maintenance and unified look and feel
      of all AMCC boards.
      Signed-off-by: Stefan Roese's avatarStefan Roese <sr@denx.de>
      490f2040
  15. 03 Jun, 2008 2 commits
    • Stefan Roese's avatar
      ppc4xx: Change Kilauea to use the common DDR2 init function · ec724f88
      Stefan Roese authored
      
      
      This patch changes the kilauea and kilauea_nand (for NAND booting)
      board port to not use a board specific DDR2 init routine anymore. Now
      the common code from cpu/ppc4xx is used.
      
      Thanks to Grant Erickson for all his basic work on this 405EX early
      bootup.
      Signed-off-by: Stefan Roese's avatarStefan Roese <sr@denx.de>
      ec724f88
    • Grant Erickson's avatar
      ppc4xx: Enable Primordial Stack for 40x and Unify ECC Handling · 8a24c07b
      Grant Erickson authored and Stefan Roese's avatar Stefan Roese committed
      
      
      This patch (Part 2 of 2):
      
      * Rolls up a suite of changes to enable correct primordial stack and
        global data handling when the data cache is used for such a purpose
        for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS).
      
      * Related to the first, unifies DDR2 SDRAM and ECC initialization by
        eliminating redundant ECC initialization implementations and moving
        redundant SDRAM initialization out of board code into shared 4xx
        code.
      
      * Enables MCSR visibility on the 405EX(r).
      
      * Enables the use of the data cache for initial RAM on
        both AMCC's Kilauea and Makalu and removes a redundant
        CFG_POST_MEMORY flag from each board's CONFIG_POST value.
      
        - Removed, per Stefan Roese's request, defunct memory.c file for
          Makalu and rolled sdram_init from it into makalu.c.
      
      With respect to the 4xx DDR initialization and ECC unification, there
      is certainly more work that can and should be done (file renaming,
      etc.). However, that can be handled at a later date on a second or
      third pass. As it stands, this patch moves things forward in an
      incremental yet positive way for those platforms that utilize this
      code and the features associated with it.
      Signed-off-by: default avatarGrant Erickson <gerickson@nuovations.com>
      Signed-off-by: Stefan Roese's avatarStefan Roese <sr@denx.de>
      8a24c07b
  16. 20 May, 2008 1 commit
    • Wolfgang Denk's avatar
      Big white-space cleanup. · 53677ef1
      Wolfgang Denk authored
      
      
      This commit gets rid of a huge amount of silly white-space issues.
      Especially, all sequences of SPACEs followed by TAB characters get
      removed (unless they appear in print statements).
      
      Also remove all embedded "vim:" and "vi:" statements which hide
      indentation problems.
      Signed-off-by: Wolfgang Denk's avatarWolfgang Denk <wd@denx.de>
      53677ef1
  17. 10 May, 2008 1 commit
  18. 08 May, 2008 1 commit
  19. 11 Apr, 2008 1 commit
  20. 03 Mar, 2008 1 commit
  21. 17 Jan, 2008 1 commit
  22. 27 Dec, 2007 2 commits
  23. 13 Dec, 2007 1 commit
  24. 08 Dec, 2007 1 commit
  25. 27 Nov, 2007 1 commit
  26. 26 Nov, 2007 1 commit
  27. 17 Nov, 2007 1 commit
  28. 09 Nov, 2007 1 commit
  29. 03 Nov, 2007 1 commit
  30. 31 Oct, 2007 5 commits