1. 25 Jan, 2010 1 commit
  2. 15 Dec, 2009 1 commit
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  5. 27 Oct, 2009 1 commit
  6. 24 Oct, 2009 1 commit
    • Tom Rix's avatar
      TI OMAP3 SDP3430: Initial Support · e63e5904
      Tom Rix authored
      
      
      Start of support of
      Texas Instruments Software Development Platform(SDP)
      for OMAP3430 - SDP3430
      
      Highlights of this platform are:
      Flash Memory devices:
      	Sibley NOR, Micron 8bit NAND and OneNAND
      Connectivity:
      	3 UARTs and expanded 4 UART ports + IrDA
      	Ethernet, USB
      Other peripherals:
      	TWL5030 PMIC+Audio+Keypad
      	VGA display
      Expansion ports:
      	Memory devices plugin boards (PISMO)
      	Connectivity board for GPS,WLAN etc.
      Completely configurable boot sequence and device mapping
      etc.
      
      Support default jumpering and:
       - UART1/ttyS0 console(legacy sdp3430 u-boot)
       - UART3/ttyS2 console (matching other boards,
      		 and SDP HW docs)
       - Ethernet
       - mmc0
       - NOR boot
      
      Currently the UART1 is enabled by default.  for
      compatibility with other OMAP3 u-boot platforms,
      enable the #define of CONSOLE_J9.
      
      Conflicts:
      
      	Makefile
      
      Fixed the conflict with smdkc100_config by moving omap_sdp3430_config
      to it is alphabetically sorted location above zoom1.
      Signed-off-by: default avatarDavid Brownell <david-b@pacbell.net>
      Signed-off-by: default avatarNishanth Menon <nm@ti.com>
      Signed-off-by: default avatarTom Rix <Tom.Rix@windriver.com>
      e63e5904
  7. 18 Oct, 2009 3 commits
  8. 16 Oct, 2009 2 commits
  9. 14 Oct, 2009 1 commit
  10. 13 Oct, 2009 3 commits
  11. 30 Sep, 2009 2 commits
    • Mingkai Hu's avatar
      On-chip ROM boot: MPC8536DS support · e40ac487
      Mingkai Hu authored
      
      
      The MPC8536E is capable of booting from the on-chip ROM - boot from
      eSDHC and boot from eSPI. When power on, the porcessor excutes the
      ROM code to initialize the eSPI/eSDHC controller, and loads the mian
      U-Boot image from the memory device that interfaced to the controller,
      such as the SDCard or SPI EEPROM, to the target memory, e.g. SDRAM or
      L2SRAM, then boot from it.
      
      The memory device should contain a specific data structure with control
      word and config word at the fixed address. The config word direct the
      process how to config the memory device, and the control word direct
      the processor where to find the image on the memory device, or where
      copy the main image to. The user can use any method to store the data
      structure to the memory device, only if store it on the assigned address.
      
      The on-chip ROM code will map the whole 4GB address space by setting
      entry0 in the TLB1, so the main image need to switch to Address space 1
      to disable this mapping and map the address space again.
      
      This patch implements loading the mian U-Boot image into L2SRAM, so
      the image can configure the system memory by using SPD EEPROM.
      Signed-off-by: default avatarMingkai Hu <Mingkai.hu@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      e40ac487
    • Mingkai Hu's avatar
      NAND boot: MPC8536DS support · 9a1a0aed
      Mingkai Hu authored
      
      
      MPC8536E can support booting from NAND flash which uses the
      image u-boot-nand.bin. This image contains two parts: a 4K
      NAND loader and a main U-Boot image. The former is appended
      to the latter to produce u-boot-nand.bin. The 4K NAND loader
      includes the corresponding nand_spl directory, along with the
      code twisted by CONFIG_NAND_SPL. The main U-Boot image just
      like a general U-Boot image except the parts that included by
      CONFIG_SYS_RAMBOOT.
      
      When power on, eLBC will automatically load from bank 0 the
      4K NAND loader into the FCM buffer RAM where CPU can execute
      the boot code directly. In the first stage, the NAND loader
      copies itself to RAM or L2SRAM to free up the FCM buffer RAM,
      then loads the main image from NAND flash to RAM or L2SRAM
      and boot from it.
      
      This patch implements the NAND loader to load the main image
      into L2SRAM, so the main image can configure the RAM by using
      SPD EEPROM. In the first stage, the NAND loader copies itself
      to the second to last 4K address space, and uses the last 4K
      address space as the initial RAM for stack.
      
      Obviously, the size of L2SRAM shouldn't be less than the size
      of the image used. If so, the workaround is to generate another
      image that includes the code to configure the RAM by SPD and
      load it to L2SRAM first, then relocate the main image to RAM
      to boot up.
      Signed-off-by: default avatarMingkai Hu <Mingkai.hu@freescale.com>
      Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
      9a1a0aed
  12. 28 Sep, 2009 1 commit
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