riscv: andes_plic: Fix riscv_get_ipi() mask

Current logic in riscv_get_ipi() for Andes PLICSW does not look
correct. The mask to test IPI pending bits for a hart should be
left shifted by (8 * gd->arch.boot_hart), just the same as what
is done in riscv_send_ipi().

Fixes: 8b3e97ba ("riscv: add functions for reading the IPI status")
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
40 jobs for master in 65 minutes and 26 seconds (queued for 3 seconds)
Status Name Job ID Coverage
  Testsuites
passed Build envtools #279914

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passed Build tools-only #279913

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passed Check for configs without MAINTAINERS entry #279912

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passed Run binman, buildman, dtoc, Kconfig and patman testsuites #279915

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passed Run tests for Nokia RX-51 (aka N900) #279916

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passed sloccount #279911

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  Test.Py
passed evb-ast2500 test.py #279921

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passed integratorcp_cm926ejs test.py #279923

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passed r2dplus_i82557c test.py #279937

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passed r2dplus_pcnet test.py #279938

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passed r2dplus_rtl8139 test.py #279939

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passed r2dplus_tulip test.py #279940

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passed sandbox_flattree test.py #279922

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passed xilinx_zynq_virt test.py #279941

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passed xtfpga test.py #279943

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  World Build
passed build all 32bit ARM platforms #279944

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passed build all 64bit ARM platforms #279945

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passed build all other platforms #279947

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passed build all PowerPC platforms #279946

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