Commit a84dab4f authored by Peng Fan's avatar Peng Fan Committed by Stefano Babic
Browse files

arm: imx8ulp: add clock support



Add i.MX8ULP clock support
Signed-off-by: Peng Fan's avatarPeng Fan <peng.fan@nxp.com>
parent 166bc7fb
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2021 NXP
*/
#ifndef _ASM_ARCH_CGC_H
#define _ASM_ARCH_CGC_H
enum cgc1_clk {
DUMMY0_CLK,
DUMMY1_CLK,
LPOSC,
XBAR_BUSCLK,
SOSC,
SOSC_DIV1,
SOSC_DIV2,
SOSC_DIV3,
FRO,
FRO_DIV1,
FRO_DIV2,
FRO_DIV3,
PLL2,
PLL3,
PLL3_VCODIV,
PLL3_PFD0,
PLL3_PFD1,
PLL3_PFD2,
PLL3_PFD3,
PLL3_PFD0_DIV1,
PLL3_PFD0_DIV2,
PLL3_PFD1_DIV1,
PLL3_PFD1_DIV2,
PLL3_PFD2_DIV1,
PLL3_PFD2_DIV2,
PLL3_PFD3_DIV1,
PLL3_PFD3_DIV2,
};
struct cgc1_regs {
u32 verid;
u32 rsvd1[4];
u32 ca35clk;
u32 rsvd2[2];
u32 clkoutcfg;
u32 rsvd3[4];
u32 nicclk;
u32 xbarclk;
u32 rsvd4[21];
u32 clkdivrst;
u32 rsvd5[29];
u32 soscdiv;
u32 rsvd6[63];
u32 frodiv;
u32 rsvd7[189];
u32 pll2csr;
u32 rsvd8[3];
u32 pll2cfg;
u32 rsvd9;
u32 pll2denom;
u32 pll2num;
u32 pll2ss;
u32 rsvd10[55];
u32 pll3csr;
u32 pll3div_vco;
u32 pll3div_pfd0;
u32 pll3div_pfd1;
u32 pll3cfg;
u32 pll3pfdcfg;
u32 pll3denom;
u32 pll3num;
u32 pll3ss;
u32 pll3lock;
u32 rsvd11[54];
u32 enetstamp;
u32 rsvd12[67];
u32 pllusbcfg;
u32 rsvd13[59];
u32 aud_clk1;
u32 sai5_4_clk;
u32 tpm6_7clk;
u32 mqs1clk;
u32 rsvd14[60];
u32 lvdscfg;
};
struct cgc2_regs {
u32 verid;
u32 rsvd1[4];
u32 hificlk;
u32 rsvd2[2];
u32 clkoutcfg;
u32 rsvd3[6];
u32 niclpavclk;
u32 ddrclk;
u32 rsvd4[19];
u32 clkdivrst;
u32 rsvd5[29];
u32 soscdiv;
u32 rsvd6[63];
u32 frodiv;
u32 rsvd7[253];
u32 pll4csr;
u32 pll4div_vco;
u32 pll4div_pfd0;
u32 pll4div_pfd1;
u32 pll4cfg;
u32 pll4pfdcfg;
u32 pll4denom;
u32 pll4num;
u32 pll4ss;
u32 pll4lock;
u32 rsvd8[128];
u32 aud_clk2;
u32 sai7_6_clk;
u32 tpm8clk;
u32 rsvd9[1];
u32 spdifclk;
u32 rsvd10[59];
u32 lvdscfg;
};
u32 cgc1_clk_get_rate(enum cgc1_clk clk);
void cgc1_pll3_init(void);
void cgc1_pll2_init(void);
void cgc1_soscdiv_init(void);
void cgc1_init_core_clk(void);
void cgc2_pll4_init(void);
void cgc2_ddrclk_config(u32 src, u32 div);
u32 cgc1_sosc_div(enum cgc1_clk clk);
#endif
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2020 NXP
* Copyright 2021 NXP
*/
#ifndef _ASM_ARCH_IMX8ULP_CLOCK_H
......@@ -17,6 +17,7 @@ enum mxc_clock {
MXC_DDR_CLK,
MXC_ESDHC_CLK,
MXC_ESDHC2_CLK,
MXC_ESDHC3_CLK,
MXC_I2C_CLK,
};
......@@ -26,9 +27,15 @@ u32 get_lpuart_clk(void);
int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
u32 imx_get_i2cclk(unsigned int i2c_num);
#endif
void enable_usboh3_clk(unsigned char enable);
int enable_usb_pll(ulong usb_phy_base);
#ifdef CONFIG_MXC_OCOTP
void enable_ocotp_clk(unsigned char enable);
#endif
void init_clk_usdhc(u32 index);
void init_clk_fspi(int index);
void init_clk_ddr(void);
int set_ddr_clk(u32 phy_freq_mhz);
void clock_init(void);
void cgc1_enet_stamp_sel(u32 clk_src);
#endif
......@@ -7,6 +7,7 @@
#define _IMX8ULP_REGS_H_
#define ARCH_MXC
#include <linux/bitops.h>
#include <linux/sizes.h>
#define PBRIDGE0_BASE 0x28000000
......
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2021 NXP
*/
#ifndef _ASM_ARCH_IMX8ULP_PCC_H
#define _ASM_ARCH_IMX8ULP_PCC_H
#include <asm/arch/cgc.h>
enum pcc3_entry {
DMA1_MP_PCC3_SLOT = 1,
DMA1_CH0_PCC3_SLOT = 2,
DMA1_CH1_PCC3_SLOT = 3,
DMA1_CH2_PCC3_SLOT = 4,
DMA1_CH3_PCC3_SLOT = 5,
DMA1_CH4_PCC3_SLOT = 6,
DMA1_CH5_PCC3_SLOT = 7,
DMA1_CH6_PCC3_SLOT = 8,
DMA1_CH7_PCC3_SLOT = 9,
DMA1_CH8_PCC3_SLOT = 10,
DMA1_CH9_PCC3_SLOT = 11,
DMA1_CH10_PCC3_SLOT = 12,
DMA1_CH11_PCC3_SLOT = 13,
DMA1_CH12_PCC3_SLOT = 14,
DMA1_CH13_PCC3_SLOT = 15,
DMA1_CH14_PCC3_SLOT = 16,
DMA1_CH15_PCC3_SLOT = 17,
DMA1_CH16_PCC3_SLOT = 18,
DMA1_CH17_PCC3_SLOT = 19,
DMA1_CH18_PCC3_SLOT = 20,
DMA1_CH19_PCC3_SLOT = 21,
DMA1_CH20_PCC3_SLOT = 22,
DMA1_CH21_PCC3_SLOT = 23,
DMA1_CH22_PCC3_SLOT = 24,
DMA1_CH23_PCC3_SLOT = 25,
DMA1_CH24_PCC3_SLOT = 26,
DMA1_CH25_PCC3_SLOT = 27,
DMA1_CH26_PCC3_SLOT = 28,
DMA1_CH27_PCC3_SLOT = 29,
DMA1_CH28_PCC3_SLOT = 30,
DMA1_CH29_PCC3_SLOT = 31,
DMA1_CH30_PCC3_SLOT = 32,
DMA1_CH31_PCC3_SLOT = 33,
MU0_B_PCC3_SLOT = 34,
MU3_A_PCC3_SLOT = 35,
LLWU1_PCC3_SLOT = 38,
UPOWER_PCC3_SLOT = 40,
WDOG3_PCC3_SLOT = 42,
WDOG4_PCC3_SLOT = 43,
XRDC_MGR_PCC3_SLOT = 47,
SEMA42_1_PCC3_SLOT = 48,
ROMCP1_PCC3_SLOT = 49,
LPIT1_PCC3_SLOT = 50,
TPM4_PCC3_SLOT = 51,
TPM5_PCC3_SLOT = 52,
FLEXIO1_PCC3_SLOT = 53,
I3C2_PCC3_SLOT = 54,
LPI2C4_PCC3_SLOT = 55,
LPI2C5_PCC3_SLOT = 56,
LPUART4_PCC3_SLOT = 57,
LPUART5_PCC3_SLOT = 58,
LPSPI4_PCC3_SLOT = 59,
LPSPI5_PCC3_SLOT = 60,
};
enum pcc4_entry {
FLEXSPI2_PCC4_SLOT = 1,
TPM6_PCC4_SLOT = 2,
TPM7_PCC4_SLOT = 3,
LPI2C6_PCC4_SLOT = 4,
LPI2C7_PCC4_SLOT = 5,
LPUART6_PCC4_SLOT = 6,
LPUART7_PCC4_SLOT = 7,
SAI4_PCC4_SLOT = 8,
SAI5_PCC4_SLOT = 9,
PCTLE_PCC4_SLOT = 10,
PCTLF_PCC4_SLOT = 11,
SDHC0_PCC4_SLOT = 13,
SDHC1_PCC4_SLOT = 14,
SDHC2_PCC4_SLOT = 15,
USB0_PCC4_SLOT = 16,
USBPHY_PCC4_SLOT = 17,
USB1_PCC4_SLOT = 18,
USB1PHY_PCC4_SLOT = 19,
USB_XBAR_PCC4_SLOT = 20,
ENET_PCC4_SLOT = 21,
SFA1_PCC4_SLOT = 22,
RGPIOE_PCC4_SLOT = 30,
RGPIOF_PCC4_SLOT = 31,
};
/* PCC registers */
#define PCC_PR_OFFSET 31
#define PCC_PR_MASK (0x1 << PCC_PR_OFFSET)
#define PCC_CGC_OFFSET 30
#define PCC_CGC_MASK (0x1 << PCC_CGC_OFFSET)
#define PCC_INUSE_OFFSET 29
#define PCC_INUSE_MASK (0x1 << PCC_INUSE_OFFSET)
#define PCC_PCS_OFFSET 24
#define PCC_PCS_MASK (0x7 << PCC_PCS_OFFSET)
#define PCC_FRAC_OFFSET 3
#define PCC_FRAC_MASK (0x1 << PCC_FRAC_OFFSET)
#define PCC_PCD_OFFSET 0
#define PCC_PCD_MASK (0x7 << PCC_PCD_OFFSET)
enum pcc_clksrc_type {
CLKSRC_PER_PLAT = 0,
CLKSRC_PER_BUS = 1,
CLKSRC_NO_PCS = 2,
};
enum pcc_div_type {
PCC_HAS_DIV,
PCC_NO_DIV,
};
enum pcc_rst_b {
PCC_HAS_RST_B,
PCC_NO_RST_B,
};
/* This structure keeps info for each pcc slot */
struct pcc_entry {
u32 pcc_base;
u32 pcc_slot;
enum pcc_clksrc_type clksrc;
enum pcc_div_type div;
enum pcc_rst_b rst_b;
};
int pcc_clock_enable(int pcc_controller, int pcc_clk_slot, bool enable);
int pcc_clock_sel(int pcc_controller, int pcc_clk_slot, enum cgc1_clk src);
int pcc_clock_div_config(int pcc_controller, int pcc_clk_slot, bool frac, u8 div);
bool pcc_clock_is_enable(int pcc_controller, int pcc_clk_slot);
int pcc_clock_get_clksrc(int pcc_controller, int pcc_clk_slot, enum cgc1_clk *src);
int pcc_reset_peripheral(int pcc_controller, int pcc_clk_slot, bool reset);
u32 pcc_clock_get_rate(int pcc_controller, int pcc_clk_slot);
#endif
......@@ -4,4 +4,4 @@
#
obj-y += lowlevel_init.o
obj-y += soc.o clock.o iomux.o
obj-y += soc.o clock.o iomux.o pcc.o cgc.o
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 NXP
*/
#include <common.h>
#include <div64.h>
#include <asm/io.h>
#include <errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/cgc.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
static struct cgc1_regs *cgc1_regs = (struct cgc1_regs *)0x292C0000UL;
static struct cgc2_regs *cgc2_regs = (struct cgc2_regs *)0x2da60000UL;
void cgc1_soscdiv_init(void)
{
/* Configure SOSC/FRO DIV1 ~ DIV3 */
clrbits_le32(&cgc1_regs->soscdiv, BIT(7));
clrbits_le32(&cgc1_regs->soscdiv, BIT(15));
clrbits_le32(&cgc1_regs->soscdiv, BIT(23));
clrbits_le32(&cgc1_regs->soscdiv, BIT(31));
clrbits_le32(&cgc1_regs->frodiv, BIT(7));
}
void cgc1_pll2_init(void)
{
u32 reg;
if (readl(&cgc1_regs->pll2csr) & BIT(23))
clrbits_le32(&cgc1_regs->pll2csr, BIT(23));
/* Disable PLL2 */
clrbits_le32(&cgc1_regs->pll2csr, BIT(0));
mdelay(1);
/* wait valid bit false */
while ((readl(&cgc1_regs->pll2csr) & BIT(24)))
;
/* Select SOSC as source, freq = 31 * 24 =744mhz */
reg = 31 << 16;
writel(reg, &cgc1_regs->pll2cfg);
/* Enable PLL2 */
setbits_le32(&cgc1_regs->pll2csr, BIT(0));
/* Wait for PLL2 clock ready */
while (!(readl(&cgc1_regs->pll2csr) & BIT(24)))
;
}
static void cgc1_set_a35_clk(u32 clk_src, u32 div_core)
{
u32 reg;
/* ulock */
if (readl(&cgc1_regs->ca35clk) & BIT(31))
clrbits_le32(&cgc1_regs->ca35clk, BIT(31));
reg = readl(&cgc1_regs->ca35clk);
reg &= ~GENMASK(29, 21);
reg |= ((clk_src & 0x3) << 28);
reg |= (((div_core - 1) & 0x3f) << 21);
writel(reg, &cgc1_regs->ca35clk);
while (!(readl(&cgc1_regs->ca35clk) & BIT(27)))
;
}
void cgc1_init_core_clk(void)
{
u32 reg = readl(&cgc1_regs->ca35clk);
/* if already selected to PLL2, switch to FRO firstly */
if (((reg >> 28) & 0x3) == 0x1)
cgc1_set_a35_clk(0, 1);
/* Set pll2 to 750Mhz for 1V */
cgc1_pll2_init();
/* Set A35 clock to pll2 */
cgc1_set_a35_clk(1, 1);
}
void cgc1_enet_stamp_sel(u32 clk_src)
{
writel((clk_src & 0x7) << 24, &cgc1_regs->enetstamp);
}
void cgc1_pll3_init(void)
{
/* Gate off VCO */
setbits_le32(&cgc1_regs->pll3div_vco, BIT(7));
/* Disable PLL3 */
clrbits_le32(&cgc1_regs->pll3csr, BIT(0));
/* Gate off PFDxDIV */
setbits_le32(&cgc1_regs->pll3div_pfd0, BIT(7) | BIT(15) | BIT(23) | BIT(31));
setbits_le32(&cgc1_regs->pll3div_pfd1, BIT(7) | BIT(15) | BIT(23) | BIT(31));
/* Gate off PFDx */
setbits_le32(&cgc1_regs->pll3pfdcfg, BIT(7));
setbits_le32(&cgc1_regs->pll3pfdcfg, BIT(15));
setbits_le32(&cgc1_regs->pll3pfdcfg, BIT(23));
setbits_le32(&cgc1_regs->pll3pfdcfg, BIT(31));
/* Select SOSC as source */
clrbits_le32(&cgc1_regs->pll3cfg, BIT(0));
//setbits_le32(&cgc1_regs->pll3cfg, 22 << 16);
writel(22 << 16, &cgc1_regs->pll3cfg);
writel(578, &cgc1_regs->pll3num);
writel(1000, &cgc1_regs->pll3denom);
/* Enable PLL3 */
setbits_le32(&cgc1_regs->pll3csr, BIT(0));
/* Wait for PLL3 clock ready */
while (!(readl(&cgc1_regs->pll3csr) & BIT(24)))
;
/* Gate on VCO */
clrbits_le32(&cgc1_regs->pll3div_vco, BIT(7));
/*
* PFD0: 380MHz/396/396/328
*/
clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F);
setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 0);
clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(7));
while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(6)))
;
clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 8);
setbits_le32(&cgc1_regs->pll3pfdcfg, 24 << 8);
clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(15));
while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(14)))
;
clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 16);
setbits_le32(&cgc1_regs->pll3pfdcfg, 24 << 16);
clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(23));
while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(22)))
;
clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 24);
setbits_le32(&cgc1_regs->pll3pfdcfg, 29 << 24);
clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(31));
while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(30)))
;
clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(7));
clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(15));
clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(23));
clrbits_le32(&cgc1_regs->pll3div_pfd0, BIT(31));
clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(7));
clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(15));
clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(23));
clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(31));
}
void cgc2_pll4_init(void)
{
/* Disable PFD DIV and clear DIV */
writel(0x80808080, &cgc2_regs->pll4div_pfd0);
writel(0x80808080, &cgc2_regs->pll4div_pfd1);
/* Gate off and clear PFD */
writel(0x80808080, &cgc2_regs->pll4pfdcfg);
/* Disable PLL4 */
writel(0x0, &cgc2_regs->pll4csr);
/* Configure PLL4 to 528Mhz and clock source from SOSC */
writel(22 << 16, &cgc2_regs->pll4cfg);
writel(0x1, &cgc2_regs->pll4csr);
/* wait for PLL4 output valid */
while (!(readl(&cgc2_regs->pll4csr) & BIT(24)))
;
/* Enable all 4 PFDs */
setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 0); /* 316.8Mhz for NIC_LPAV */
setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 8);
setbits_le32(&cgc2_regs->pll4pfdcfg, 12 << 16);
setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 24);
clrbits_le32(&cgc2_regs->pll4pfdcfg, BIT(7) | BIT(15) | BIT(23) | BIT(31));
while ((readl(&cgc2_regs->pll4pfdcfg) & (BIT(30) | BIT(22) | BIT(14) | BIT(6)))
!= (BIT(30) | BIT(22) | BIT(14) | BIT(6)))
;
/* Enable PFD DIV */
clrbits_le32(&cgc2_regs->pll4div_pfd0, BIT(7) | BIT(15) | BIT(23) | BIT(31));
clrbits_le32(&cgc2_regs->pll4div_pfd1, BIT(7) | BIT(15) | BIT(23) | BIT(31));
}
void cgc2_ddrclk_config(u32 src, u32 div)
{
writel((src << 28) | (div << 21), &cgc2_regs->ddrclk);
/* wait for DDRCLK switching done */
while (!(readl(&cgc2_regs->ddrclk) & BIT(27)))
;
}
u32 decode_pll(enum cgc1_clk pll)
{
u32 reg, infreq, mult;
u32 num, denom;
infreq = 24000000U;
/*
* Alought there are four choices for the bypass src,
* we choose SOSC 24M which is the default set in ROM.
* TODO: check more the comments
*/
switch (pll) {
case PLL2:
reg = readl(&cgc1_regs->pll2csr);
if (!(reg & BIT(24)))
return 0;
reg = readl(&cgc1_regs->pll2cfg);
mult = (reg >> 16) & 0x7F;
denom = readl(&cgc1_regs->pll2denom) & 0x3FFFFFFF;
num = readl(&cgc1_regs->pll2num) & 0x3FFFFFFF;
return (u64)infreq * mult + (u64)infreq * num / denom;
case PLL3:
reg = readl(&cgc1_regs->pll3csr);
if (!(reg & BIT(24)))
return 0;
reg = readl(&cgc1_regs->pll3cfg);
mult = (reg >> 16) & 0x7F;
denom = readl(&cgc1_regs->pll3denom) & 0x3FFFFFFF;
num = readl(&cgc1_regs->pll3num) & 0x3FFFFFFF;
return (u64)infreq * mult + (u64)infreq * num / denom;
default:
printf("Unsupported pll clocks %d\n", pll);
break;
}
return 0;
}
u32 cgc1_pll3_vcodiv_rate(void)
{
u32 reg, gate, div;
reg = readl(&cgc1_regs->pll3div_vco);
gate = BIT(7) & reg;
div = reg & 0x3F;
return gate ? 0 : decode_pll(PLL3) / (div + 1);
}
u32 cgc1_pll3_pfd_rate(enum cgc1_clk clk)
{
u32 index, gate, vld, reg;
switch (clk) {
case PLL3_PFD0:
index = 0;
break;
case PLL3_PFD1:
index = 1;
break;
case PLL3_PFD2:
index = 2;
break;
case PLL3_PFD3:
index = 3;
break;
default:
return 0;
}
reg = readl(&cgc1_regs->pll3pfdcfg);
gate = reg & (BIT(7) << (index * 8));
vld = reg & (BIT(6) << (index * 8));
if (gate || !vld)
return 0;
return (u64)decode_pll(PLL3) * 18 / ((reg >> (index * 8)) & 0x3F);
}