Commit 18f4e858 authored by Tom Rini's avatar Tom Rini
Browse files

Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq

fsl-qoriq: Fixes related to env, spi, usb, crypto, configs, distro-boot
for Layerscape Boards like lx2, sl28, ls2088ardb.
powerpc: Fixes for t208xrdb revd board and cortina related configs
update for T208xRDB, T4240RDB.
parents 926fe46a 760ca92d
......@@ -58,6 +58,7 @@ config ARCH_LS1043A
select ARM_ERRATA_855873 if !TFABOOT
select FSL_LAYERSCAPE
select FSL_LSCH2
select HAS_FSL_XHCI_USB if USB_HOST
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
......@@ -89,6 +90,7 @@ config ARCH_LS1046A
select ARMV8_SET_SMPEN
select FSL_LAYERSCAPE
select FSL_LSCH2
select HAS_FSL_XHCI_USB if USB_HOST
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
......@@ -245,6 +247,7 @@ config ARCH_LX2160A
bool
select ARMV8_SET_SMPEN
select FSL_LSCH3
select HAS_FSL_XHCI_USB if USB_HOST
select NXP_LSCH3_2
select SYS_HAS_SERDES
select SYS_FSL_SRDS_1
......@@ -642,9 +645,8 @@ config SPL_LDSCRIPT
config HAS_FSL_XHCI_USB
bool
default y if ARCH_LS1043A || ARCH_LS1046A
help
For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
For some SoC (such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
pins, select it when the pins are assigned to USB.
config SYS_FSL_BOOTROM_BASE
......
......@@ -953,12 +953,15 @@ int board_late_init(void)
#endif
#ifdef CONFIG_TFABOOT
/*
* Set bootcmd and mcinitcmd if they don't exist in the environment.
* Set bootcmd and mcinitcmd if "fsl_bootcmd_mcinitcmd_set" does
* not exists in env
*/
if (!env_get("bootcmd"))
if (env_get_yesno("fsl_bootcmd_mcinitcmd_set") <= 0) {
// Set bootcmd and mcinitcmd as per boot source
fsl_setenv_bootcmd();
if (!env_get("mcinitcmd"))
fsl_setenv_mcinitcmd();
env_set("fsl_bootcmd_mcinitcmd_set", "y");
}
#endif
#ifdef CONFIG_QSPI_AHB_INIT
qspi_ahb_init();
......
......@@ -72,61 +72,6 @@
/* The following setting enables 1-1-2 (CMD-ADDR-DATA) mode */
spi-rx-bus-width = <2>; /* 2 SPI Rx lines */
spi-tx-bus-width = <1>; /* 1 SPI Tx line */
partition@0 {
reg = <0x000000 0x010000>;
label = "rcw";
read-only;
};
partition@10000 {
reg = <0x010000 0x0f0000>;
label = "failsafe bootloader";
read-only;
};
partition@100000 {
reg = <0x100000 0x040000>;
label = "failsafe DP firmware";
read-only;
};
partition@140000 {
reg = <0x140000 0x0a0000>;
label = "failsafe trusted firmware";
read-only;
};
partition@1e0000 {
reg = <0x1e0000 0x020000>;
label = "reserved";
read-only;
};
partition@200000 {
reg = <0x200000 0x010000>;
label = "configuration store";
};
partition@210000 {
reg = <0x210000 0x0f0000>;
label = "bootloader";
};
partition@300000 {
reg = <0x300000 0x040000>;
label = "DP firmware";
};
partition@340000 {
reg = <0x340000 0x0a0000>;
label = "trusted firmware";
};
partition@3e0000 {
reg = <0x3e0000 0x020000>;
label = "bootloader environment";
};
};
};
......
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
*/
#include <common.h>
......@@ -498,8 +499,11 @@ static int calc_img_key_hash(struct fsl_secboot_img_priv *img)
return ret;
ret = algo->hash_init(algo, &ctx);
if (ret)
if (ret) {
if (ctx)
free(ctx);
return ret;
}
/* Update hash for ESBC key */
#ifdef CONFIG_KEY_REVOCATION
......@@ -518,8 +522,11 @@ static int calc_img_key_hash(struct fsl_secboot_img_priv *img)
/* Copy hash at destination buffer */
ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size);
if (ret)
if (ret) {
if (ctx)
free(ctx);
return ret;
}
for (i = 0; i < SHA256_BYTES; i++)
img->img_key_hash[i] = hash_val[i];
......@@ -547,14 +554,18 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img)
ret = algo->hash_init(algo, &ctx);
/* Copy hash at destination buffer */
if (ret)
if (ret) {
free(ctx);
return ret;
}
/* Update hash for CSF Header */
ret = algo->hash_update(algo, ctx,
(u8 *)&img->hdr, sizeof(struct fsl_secboot_img_hdr), 0);
if (ret)
if (ret) {
free(ctx);
return ret;
}
/* Update the hash with that of srk table if srk flag is 1
* If IE Table is selected, key is not added in the hash
......@@ -581,22 +592,29 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img)
key_hash = 1;
}
#endif
if (ret)
if (ret) {
free(ctx);
return ret;
if (!key_hash)
}
if (!key_hash) {
free(ctx);
return ERROR_KEY_TABLE_NOT_FOUND;
}
/* Update hash for actual Image */
ret = algo->hash_update(algo, ctx,
(u8 *)(*(img->img_addr_ptr)), img->img_size, 1);
if (ret)
if (ret) {
free(ctx);
return ret;
}
/* Copy hash at destination buffer */
ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size);
if (ret)
if (ret) {
free(ctx);
return ret;
}
return 0;
}
......
......@@ -33,6 +33,9 @@
#endif
#include "../common/vid.h"
#define CORTINA_FW_ADDR_IFCNOR 0x580980000
#define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0x584980000
#define CORTINA_FW_ADDR_QSPI 0x980000
#define PIN_MUX_SEL_SDHC 0x00
#define PIN_MUX_SEL_DSPI 0x0a
......@@ -235,6 +238,41 @@ int config_board_mux(int ctrl_type)
return 0;
}
ulong *cs4340_get_fw_addr(void)
{
#ifdef CONFIG_TFABOOT
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 svr = gur_in32(&gur->svr);
#endif
ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR;
#ifdef CONFIG_TFABOOT
/* LS2088A TFA boot */
if (SVR_SOC_VER(svr) == SVR_LS2088A) {
enum boot_src src = get_boot_src();
u8 sw;
switch (src) {
case BOOT_SOURCE_IFC_NOR:
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & 0x0f);
if (sw == 0)
cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR;
else if (sw == 4)
cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK;
break;
case BOOT_SOURCE_QSPI_NOR:
/* Only one bank in QSPI */
cortina_fw_addr = CORTINA_FW_ADDR_QSPI;
break;
default:
printf("WARNING: Boot source not found\n");
}
}
#endif
return (ulong *)cortina_fw_addr;
}
int board_init(void)
{
#ifdef CONFIG_FSL_MC_ENET
......
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor
* Copyright 2021 NXP
*/
/*
......@@ -42,3 +43,6 @@ void cpld_write(unsigned int reg, u8 value);
/* RSTCON Register */
#define CPLD_RSTCON_EDC_RST 0x04
/* MISCCSR Register */
#define CPLD_MISC_POR_EN 0x30
......@@ -128,6 +128,13 @@ int misc_init_r(void)
reg |= CPLD_RSTCON_EDC_RST;
CPLD_WRITE(reset_ctl, reg);
/* Enable POR for boards revisions D and up */
if (get_hw_revision() >= 'D') {
reg = CPLD_READ(misc_csr);
reg |= CPLD_MISC_POR_EN;
CPLD_WRITE(misc_csr, reg);
}
return 0;
}
......@@ -158,3 +165,23 @@ int ft_board_setup(void *blob, struct bd_info *bd)
return 0;
}
ulong *cs4340_get_fw_addr(void)
{
ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR;
#ifdef CONFIG_SYS_CORTINA_FW_IN_NOR
u8 reg;
reg = CPLD_READ(flash_csr);
if (!(reg & CPLD_BOOT_SEL)) {
reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
if (reg == 0)
cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR;
else if (reg == 4)
cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK;
}
#endif
return (ulong *)cortina_fw_addr;
}
......@@ -7,6 +7,9 @@
#ifndef __CORENET_DS_H__
#define __CORENET_DS_H__
#define CORTINA_FW_ADDR_IFCNOR 0xefe00000
#define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebe00000
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, struct bd_info *bd);
void fdt_fixup_board_fman_ethernet(void *blob);
......
......@@ -151,3 +151,22 @@ void board_detail(void)
break;
}
}
ulong *cs4340_get_fw_addr(void)
{
ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR;
#ifdef CONFIG_SYS_CORTINA_FW_IN_NOR
u8 sw;
sw = CPLD_READ(vbank);
sw = sw & CPLD_BANK_SEL_MASK;
if (sw == 0)
cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR;
else if (sw == 4)
cortina_fw_addr = CORTINA_FW_ADDR_IFCNOR_ALTBANK;
#endif
return (ulong *)cortina_fw_addr;
}
......@@ -11,6 +11,9 @@
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM2_DTSEC 4
#define CORTINA_FW_ADDR_IFCNOR 0xefe00000
#define CORTINA_FW_ADDR_IFCNOR_ALTBANK 0xebf00000
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, struct bd_info *bd);
......
......@@ -69,6 +69,7 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_FW_IN_NAND=y
CONFIG_CORTINA_FW_ADDR=0x200000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
......
......@@ -66,6 +66,7 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_FW_IN_MMC=y
CONFIG_CORTINA_FW_ADDR=0x114000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
......
......@@ -68,6 +68,7 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_FW_IN_SPIFLASH=y
CONFIG_CORTINA_FW_ADDR=0x120000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
......
......@@ -53,6 +53,7 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0xEFE00000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
......
......@@ -70,6 +70,7 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_FW_IN_NAND=y
CONFIG_CORTINA_FW_ADDR=0x200000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
......
......@@ -67,6 +67,7 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_FW_IN_MMC=y
CONFIG_CORTINA_FW_ADDR=0x114000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
......
......@@ -69,6 +69,7 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_SYS_CORTINA_FW_IN_SPIFLASH=y
CONFIG_CORTINA_FW_ADDR=0x120000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
......
......@@ -54,6 +54,7 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0xEFE00000
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
......
......@@ -57,6 +57,7 @@ CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0x77f000
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
......
......@@ -45,6 +45,7 @@ CONFIG_SPI_FLASH_SST=y
CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_CORTINA=y
CONFIG_CORTINA_FW_ADDR=0xefe00000
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
......
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