1. 12 Jul, 2018 21 commits
    • Marek Vasut's avatar
      FIXME: ARM: socfpga: Unreset both UARTs to avoid complexity · f35ed111
      Marek Vasut authored
      
      
      Unreset both UART blocks to get rid of the obscure complexity.
      This needs to be superseded by reset controller driver.
      
      Signed-off-by: Marek Vasut's avatarMarek Vasut <marex@denx.de>
      f35ed111
    • Marek Vasut's avatar
      FIXME: ARM: socfpga: Ungate resets for Arria10 SoCDK · 0722aa6e
      Marek Vasut authored
      
      
      Ungate the peripheral resets on A10 SoCDK. This should be done using the
      reset manager, but since it is not implemented yet, for peripherals out
      of reset manually to get I2C and ethernet working.
      
      Signed-off-by: Marek Vasut's avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <chin.liang.see@intel.com>
      Cc: Dinh Nguyen <dinguyen@kernel.org>
      0722aa6e
    • Marek Vasut's avatar
      ARM: socfpga: Init missing security policies on A10 · e9fa1c7b
      Marek Vasut authored
      
      
      The Arria10 requires proper configuration of the NOC firewall, otherwise
      the access to certain areas of the LWHPS bridge fails in Linux. Add the
      missing setup.
      
      Signed-off-by: Marek Vasut's avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <chin.liang.see@intel.com>
      Cc: Dinh Nguyen <dinguyen@kernel.org>
      e9fa1c7b
    • Marek Vasut's avatar
      ARM: socfpga: Set up the HPS-FPGA pin multiplexing · 1aab6014
      Marek Vasut authored
      
      
      Set up the pin multiplexing of the FPGA pins used by HPS peripherals
      on Arria10. This has to happen after the DRAM was brought up.
      
      Signed-off-by: Marek Vasut's avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <chin.liang.see@intel.com>
      Cc: Dinh Nguyen <dinguyen@kernel.org>
      1aab6014
    • Marek Vasut's avatar
      ARM: socfpga: Add bridge enable/disable command · ce68fb57
      Marek Vasut authored
      
      
      Add command to enable/disable bridges just like on Gen5.
      
      Signed-off-by: Marek Vasut's avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <chin.liang.see@intel.com>
      Cc: Dinh Nguyen <dinguyen@kernel.org>
      ce68fb57
    • Marek Vasut's avatar
      ARM: socfpga: Synchronize the configuration for A10 SoCDK · e5385cae
      Marek Vasut authored
      
      
      Update the default configuration file to enable the necessary functionality
      the get the kit working. That includes fitImage loading in SPL, SPL SD/MMC
      support, USB, I2C.
      
      Signed-off-by: Marek Vasut's avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <chin.liang.see@intel.com>
      Cc: Dinh Nguyen <dinguyen@kernel.org>
      e5385cae
    • Marek Vasut's avatar
      ARM: socfpga: Add default fitImage for Arria10 SoCDK · b8a3ff99
      Marek Vasut authored
      
      
      Add default fitImage file bundling U-Boot and FPGA bitstream for Arria10.
      
      Signed-off-by: Marek Vasut's avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <chin.liang.see@intel.com>
      Cc: Dinh Nguyen <dinguyen@kernel.org>
      b8a3ff99
    • Marek Vasut's avatar
      ARM: socfpga: Use custom header target buffer in SPL · 3322afbf
      Marek Vasut authored
      
      
      Allocate buffers from OCRAM heap for the image headers in SPL on
      Arria10, since DRAM is not available at that point. This allows
      U-Boot to load the fitImage header, parse it, extract the FPGA
      bitstream section from it, program the FPGA and make DRAM available.
      
      Signed-off-by: Marek Vasut's avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <chin.liang.see@intel.com>
      Cc: Dinh Nguyen <dinguyen@kernel.org>
      3322afbf
    • Marek Vasut's avatar
      ARM: socfpga: Set default DTB address on A10 · eb32e568
      Marek Vasut authored
      
      
      Set default DT blob address on A10 SoCDK, since this SoC uses OF
      separate configuration. The 0xf0000 address is just below the text
      base and still leaves enough room for the DT to grow.
      
      Signed-off-by: Marek Vasut's avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <chin.liang.see@intel.com>
      Cc: Dinh Nguyen <dinguyen@kernel.org>
      eb32e568
    • Marek Vasut's avatar
      ARM: socfpga: Add SPL fitImage FPGA bitstream loading · 21f835eb
      Marek Vasut authored
      
      
      Add a hook implementation for loading the FPGA bitstream embedded
      in the fitImage. The FPGA image has to be loaded in smaller chunks
      as the DRAM is not available just yet. Using the fitImage mechanism
      means that loading the bitstream and loading the U-Boot image use
      exactly the same code.
      
      Signed-off-by: Marek Vasut's avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <chin.liang.see@intel.com>
      Cc: Dinh Nguyen <dinguyen@kernel.org>
      21f835eb
    • Marek Vasut's avatar
      ARM: socfpga: Add SPL fitImage config match · bd198801
      Marek Vasut authored
      
      
      Add empty SPL fitImage configuration match. This can be extended
      if there is ever need to support multiple boards with single SFP
      image.
      
      Signed-off-by: Marek Vasut's avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <chin.liang.see@intel.com>
      Cc: Dinh Nguyen <dinguyen@kernel.org>
      bd198801
    • Marek Vasut's avatar
      ARM: socfpga: Bundle U-Boot fitImage into SFP on Arria10 · f5cf70da
      Marek Vasut authored
      
      
      Bundle U-Boot fitImage containing U-Boot and FPGA bitstream into the
      u-boot-with-spl.sfp on Arria10. This lets U-Boot operate in a very
      similar fashion to Gen5, where the U-Boot binary got loaded by the
      SPL from a uImage concatenated at the end of the SPL SFP image. On
      Gen10, the U-Boot is in fitImage which contains the FPGA bitstream
      as well. In this case, the SPL can load the FPGA bitstream first and
      load the U-Boot afterward in the same manner. This is nonetheless a
      stopgap measure until there is a proper firmware loader in U-Boot.
      
      Signed-off-by: Marek Vasut's avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <chin.liang.see@intel.com>
      Cc: Dinh Nguyen <dinguyen@kernel.org>
      Cc: Tien Fong Chee <tien.fong.chee@intel.com>
      f5cf70da
    • Marek Vasut's avatar
      spl: fit: Add support for loading FPGA bitstream · 7032e30b
      Marek Vasut authored
      
      
      Add support for loading FPGA into the SPL fitImage support. The
      mechanism is flexible and allows user to override the actual
      function for loading the FPGA itself. This is because on some
      systems, the FPGA must be programmed to allow DRAM access, so
      loading the full fitImage may not be possible if it contains
      the bitstream. Instead, the spl_load_fpga_image() provides all
      the tools to load the bitstream in parts while programming it
      into the FPGA.
      
      Signed-off-by: Marek Vasut's avatarMarek Vasut <marex@denx.de>
      Cc: Tom Rini <trini@konsulko.com>
      7032e30b
    • Marek Vasut's avatar
      spl: Weed out CONFIG_SYS_TEXT_BASE usage · d7b22f74
      Marek Vasut authored
      
      
      The SPL loaders assume that the CONFIG_SYS_TEXT_BASE memory location
      is available and can be corrupted by loading ie. uImage or fitImage
      headers there. Sometimes it could be beneficial to load the headers
      elsewhere, ie. if CONFIG_SYS_TEXT_BASE is not yet writable while we
      still want to parse the image headers in some local onchip memory to
      ie. extract firmware from that image.
      
      Add the possibility to override the location where the headers get
      loaded by introducing new function, spl_get_load_buffer() which takes
      two arguments -- offset from the CONFIG_SYS_TEXT_BASE and size of the
      data that are to be loaded there -- and returns a valid buffer address
      or hangs the system. The default behavior is the same as before, add
      the offset to CONFIG_SYS_TEXT_BASE and return that address. User can
      override the weak spl_get_load_buffer() function though.
      
      Signed-off-by: Marek Vasut's avatarMarek Vasut <marex@denx.de>
      Cc: Tom Rini <trini@konsulko.com>
      d7b22f74
    • Marek Vasut's avatar
      ARM: socfpga: Assure correct CPACR configuration · 1ed500d3
      Marek Vasut authored
      
      
      Make sure the ARM CPACR register is zeroed out, this is mandatory
      on Arria10.
      
      Signed-off-by: Marek Vasut's avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <chin.liang.see@intel.com>
      Cc: Dinh Nguyen <dinguyen@kernel.org>
      1ed500d3
    • Ley Foon Tan's avatar
      arm: socfpga: Fix: Compile MCR instruction on ARM 32-bit only · d802b4b9
      Ley Foon Tan authored and Marek Vasut's avatar Marek Vasut committed
      
      
      MCR instruction only available in ARM 32-bit. So, compile MCR instruction
      when ARM 32-bit is enabled.
      
      Signed-off-by: default avatarLey Foon Tan <ley.foon.tan@intel.com>
      d802b4b9
    • Marek Vasut's avatar
      ARM: socfpga: Assure correct ACTLR configuration · 937764ab
      Marek Vasut authored
      
      
      Make sure the ARM ACTLR register has correct configuration, otherwise
      the Linux kernel refuses to boot. In particular, the "Write Full Line
      of Zeroes" bit must be cleared.
      
      Signed-off-by: Marek Vasut's avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <chin.liang.see@intel.com>
      Cc: Dinh Nguyen <dinguyen@kernel.org>
      937764ab
    • Marek Vasut's avatar
      ARM: socfpga: Make DRAM node available in SPL · 45ee7429
      Marek Vasut authored
      
      
      The SPL can also parse the DRAM configuration node to figure out the
      memory layout, make sure it is available.
      
      Signed-off-by: Marek Vasut's avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <chin.liang.see@intel.com>
      Cc: Dinh Nguyen <dinguyen@kernel.org>
      45ee7429
    • Marek Vasut's avatar
      ARM: socfpga: Pull DRAM size from DT · ab7ca05c
      Marek Vasut authored
      
      
      Pull the DRAM size from DT instead of hardcoding it into U-Boot.
      
      Signed-off-by: Marek Vasut's avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <chin.liang.see@intel.com>
      Cc: Dinh Nguyen <dinguyen@kernel.org>
      ab7ca05c
    • Marek Vasut's avatar
      ddr: altera: Add ECC DRAM scrubbing support for Arria10 · ca0897fa
      Marek Vasut authored
      
      
      The SDRAM must first be rewritten by zeroes if ECC is used to initialize
      the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a
      case. This scrubbing implementation turns the caches on temporarily, then
      overwrites the whole RAM with zeroes, flushes the caches and turns them
      off again. This provides satisfactory performance.
      
      Signed-off-by: Marek Vasut's avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <chin.liang.see@intel.com>
      Cc: Dinh Nguyen <dinguyen@kernel.org>
      ca0897fa
    • Marek Vasut's avatar
      ddr: altera: Drop custom dram_bank_mmu_setup() on Arria10 · 5f6216b6
      Marek Vasut authored
      
      
      This function was never used in SPL and the default implementation of
      dram_bank_mmu_setup() does the same thing. The only difference is the
      part which configures OCRAM as cachable, which doesn't really work as
      it covers more than the OCRAM.
      
      Signed-off-by: Marek Vasut's avatarMarek Vasut <marex@denx.de>
      Cc: Chin Liang See <chin.liang.see@intel.com>
      Cc: Dinh Nguyen <dinguyen@kernel.org>
      5f6216b6
  2. 09 Jul, 2018 1 commit
  3. 08 Jul, 2018 1 commit
  4. 06 Jul, 2018 3 commits
  5. 05 Jul, 2018 2 commits
  6. 04 Jul, 2018 1 commit
  7. 03 Jul, 2018 3 commits
  8. 02 Jul, 2018 8 commits