Commit 42dfe7a1 authored by wdenk's avatar wdenk
Browse files

Code cleanup; make several boards compile & link.

parent 855a496f
......@@ -14,7 +14,7 @@ Changes for U-Boot 1.0.2:
* Patch by Leon Kukovec, 12 Mar 2004:
Fix get_dentfromdir() to correctly handle deleted dentries
* Patch by George G. Davis, 11 Mar 2004:
Remove hard coded network settings in TI OMAP1610 H2
default board config
......
......@@ -1144,17 +1144,17 @@ ADNPESC1_base_32_config \
ADNPESC1_config: unconfig
@ >include/config.h
@[ -z "$(findstring _DNPEVA2,$@)" ] || \
{ echo "#define CONFIG_DNPEVA2 1" >>include/config.h ; \
echo "... DNP/EVA2 configuration" ; \
}
{ echo "#define CONFIG_DNPEVA2 1" >>include/config.h ; \
echo "... DNP/EVA2 configuration" ; \
}
@[ -z "$(findstring _base_32,$@)" ] || \
{ echo "#define CONFIG_NIOS_BASE_32 1" >>include/config.h ; \
echo "... NIOS 'base_32' configuration" ; \
}
{ echo "#define CONFIG_NIOS_BASE_32 1" >>include/config.h ; \
echo "... NIOS 'base_32' configuration" ; \
}
@[ -z "$(findstring ADNPESC1_config,$@)" ] || \
{ echo "#define CONFIG_NIOS_BASE_32 1" >>include/config.h ; \
echo "... NIOS 'base_32' configuration (DEFAULT)" ; \
}
{ echo "#define CONFIG_NIOS_BASE_32 1" >>include/config.h ; \
echo "... NIOS 'base_32' configuration (DEFAULT)" ; \
}
@./mkconfig -a ADNPESC1 nios nios adnpesc1 ssv
......
......@@ -235,7 +235,7 @@ int misc_init_f (void)
long int initdram (int board_type)
{
#if CONFIG_CMA111
#ifdef CONFIG_CMA111
return (32L * 1024L * 1024L);
#else
unsigned char dipsw_val;
......
......@@ -171,4 +171,3 @@ int last_stage_init(void)
return 0; /* success */
}
......@@ -45,9 +45,6 @@ unsigned long flash_init (void)
#else
unsigned long size_b0;
int i;
uint pbcr;
unsigned long base_b0;
int size_val = 0;
/* Init: no FLASHes known */
for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
......
......@@ -51,7 +51,7 @@ SECTIONS
armboot_end_data = .;
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
armboot_end = .;
_end = .;
}
......@@ -353,7 +353,7 @@ ulong flash_get_size (FPWV *addr, flash_info_t *info)
}
break;
}
/* fall thru to here ! */
default:
printf ("unknown AMD device=%x %x %x",
......
......@@ -57,7 +57,7 @@ long int initdram (int board_type)
*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN;
/* precharge all banks */
*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE;
#if CFG_DRAM_DDR
#ifdef CFG_DRAM_DDR
/* set extended mode register */
*(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_EMODE;
#endif
......
......@@ -404,7 +404,7 @@ write_data(flash_info_t * info, ulong dest, FPW data)
/* Check if Flash is (sufficiently) erased */
if ((*addr & data) != data) {
printf("not erased at %08lx (%x)\n", (ulong) addr, *addr);
printf("not erased at %08lX (%lX)\n", (ulong) addr, *addr);
return (2);
}
/* Disable interrupts which might cause a timeout here */
......
......@@ -215,7 +215,7 @@ void pci_init_board(void)
void init_ide_reset (void)
{
debug ("init_ide_reset\n");
/* Configure PSC1_4 as GPIO output for ATA reset */
*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
*(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
......
#
# image should be loaded at 0x01000000
# image should be loaded at 0x01000000
#
TEXT_BASE = 0x01000000
This diff is collapsed.
......@@ -43,8 +43,8 @@ SECTIONS
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
armboot_end_data = .;
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
armboot_end = .;
_end = .;
}
#
# image should be loaded at 0x01000000
# image should be loaded at 0x01000000
#
TEXT_BASE = 0x01000000
......@@ -107,4 +107,3 @@ int dram_init (void)
{
return 0;
}
......@@ -43,8 +43,8 @@ SECTIONS
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
armboot_end_data = .;
. = ALIGN(4);
__bss_start = .;
.bss : { *(.bss) }
armboot_end = .;
_end = .;
}
......@@ -232,7 +232,7 @@ mpl_prg_image(uchar *ld_addr)
}
puts("OK\n");
break;
#if CONFIG_BZIP2
#ifdef CONFIG_BZIP2
case IH_COMP_BZIP2:
puts("Uncompressing (BZIP2) ... ");
{
......
......@@ -474,4 +474,3 @@ int post_hotkeys_pressed(void)
return (ctrlc());
}
#endif
......@@ -351,7 +351,7 @@ void reset_phy(void)
ulong value;
/* Configure all needed port pins for GPIO */
#if CFG_ETH_MDDIS_VALUE
#ifdef CFG_ETH_MDDIS_VALUE
immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS;
#else
immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET); /* Set low */
......@@ -369,17 +369,17 @@ void reset_phy(void)
value |= CFG_PB_ETH_POWERDOWN;
/* PHY configuration includes MDDIS and CFG1 ... CFG3 */
#if CFG_ETH_CFG1_VALUE
#ifdef CFG_ETH_CFG1_VALUE
value |= CFG_PB_ETH_CFG1;
#else
value &= ~(CFG_PB_ETH_CFG1);
#endif
#if CFG_ETH_CFG2_VALUE
#ifdef CFG_ETH_CFG2_VALUE
value |= CFG_PB_ETH_CFG2;
#else
value &= ~(CFG_PB_ETH_CFG2);
#endif
#if CFG_ETH_CFG3_VALUE
#ifdef CFG_ETH_CFG3_VALUE
value |= CFG_PB_ETH_CFG3;
#else
value &= ~(CFG_PB_ETH_CFG3);
......
......@@ -309,7 +309,7 @@ void reset_phy (void)
/* Configure all needed port pins for GPIO */
#if PCU_E_WITH_SWAPPED_CS /* XXX */
# if CFG_ETH_MDDIS_VALUE
# ifdef CFG_ETH_MDDIS_VALUE
immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS;
# else
immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS); /* Set low */
......@@ -329,23 +329,23 @@ void reset_phy (void)
/* PHY configuration includes MDDIS and CFG1 ... CFG3 */
#if !PCU_E_WITH_SWAPPED_CS
# if CFG_ETH_MDDIS_VALUE
# ifdef CFG_ETH_MDDIS_VALUE
value |= CFG_PB_ETH_MDDIS;
# else
value &= ~(CFG_PB_ETH_MDDIS);
# endif
#endif
#if CFG_ETH_CFG1_VALUE
#ifdef CFG_ETH_CFG1_VALUE
value |= CFG_PB_ETH_CFG1;
#else
value &= ~(CFG_PB_ETH_CFG1);
#endif
#if CFG_ETH_CFG2_VALUE
#ifdef CFG_ETH_CFG2_VALUE
value |= CFG_PB_ETH_CFG2;
#else
value &= ~(CFG_PB_ETH_CFG2);
#endif
#if CFG_ETH_CFG3_VALUE
#ifdef CFG_ETH_CFG3_VALUE
value |= CFG_PB_ETH_CFG3;
#else
value &= ~(CFG_PB_ETH_CFG3);
......
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