Commit 46a414dc authored by wdenk's avatar wdenk

* Fix flash parameters passed to Linux for PPChameleon board

* Remove eth_init() from lib_arm/board.c; it's done in net.net.c.
parent f832d8a1
......@@ -2,6 +2,10 @@
Changes since U-Boot 1.1.1:
======================================================================
* Fix flash parameters passed to Linux for PPChameleon board
* Remove eth_init() from lib_arm/board.c; it's done in net.net.c.
* Patch by Paul Ruhland, 10 Jun 2004:
fix support for Logic SDK-LH7A404 board and clean up the
LH7A404 register macros.
......
......@@ -96,11 +96,15 @@ int misc_init_f (void)
return 0; /* dummy implementation */
}
extern flash_info_t flash_info[]; /* info for FLASH chips */
int misc_init_r (void)
{
#if 0 /* test-only */
DECLARE_GLOBAL_DATA_PTR;
/* adjust flash start and size as well as the offset */
gd->bd->bi_flashstart = 0 - flash_info[0].size;
gd->bd->bi_flashoffset= flash_info[0].size - CFG_MONITOR_LEN;
#if 0
volatile unsigned short *fpga_mode =
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
......@@ -192,8 +196,6 @@ int misc_init_r (void)
*duart0_mcr = 0x08;
*duart1_mcr = 0x08;
#endif
#endif
return (0);
}
......
......@@ -44,10 +44,10 @@ unsigned long flash_init (void)
#ifdef __DEBUG_START_FROM_SRAM__
return CFG_DUMMY_FLASH_SIZE;
#else
unsigned long size_b0;
unsigned long size;
int i;
uint pbcr;
unsigned long base_b0;
unsigned long base;
int size_val = 0;
/* Init: no FLASHes known */
......@@ -57,22 +57,22 @@ unsigned long flash_init (void)
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0<<20);
size, size<<20);
}
/* Setup offsets */
flash_get_offsets (-size_b0, &flash_info[0]);
flash_get_offsets (-size, &flash_info[0]);
/* Re-do sizing to get full correct info */
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
base_b0 = -size_b0;
switch (size_b0) {
base = -size;
switch (size) {
case 1 << 20:
size_val = 0;
break;
......@@ -89,7 +89,7 @@ unsigned long flash_init (void)
size_val = 4;
break;
}
pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
pbcr = (pbcr & 0x0001ffff) | base | (size_val << 17);
mtdcr(ebccfgd, pbcr);
/* Monitor protection ON by default */
......@@ -98,8 +98,8 @@ unsigned long flash_init (void)
0xffffffff,
&flash_info[0]);
flash_info[0].size = size_b0;
flash_info[0].size = size;
return (size_b0);
return (size);
#endif
}
......@@ -414,6 +414,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
out32 (EMAC_IAL + hw_p->hw_addr, reg);
switch (devnum) {
#if defined(CONFIG_NET_MULTI)
case 1:
/* setup MAL tx & rx channel pointers */
/* For 405EP, the EMAC1 tx channel 0 is MAL tx channel 2 */
......@@ -422,6 +423,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
/* set RX buffer size */
mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
break;
#endif
case 0:
default:
/* setup MAL tx & rx channel pointers */
......
......@@ -121,11 +121,7 @@
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0x40000000
#ifdef DEBUG
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#else
#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
#endif
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
......@@ -135,11 +131,12 @@
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
......@@ -148,6 +145,10 @@
#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
/* Address and size of Redundant Environment Sector */
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
......@@ -260,9 +261,11 @@
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
OR_SCY_5_CLK | OR_EHTR)
/*
* FLASH timing:
*/
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
OR_SCY_3_CLK | OR_EHTR | OR_BI)
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
......@@ -291,12 +294,42 @@
/*
* Memory Periodic Timer Prescaler
*
* The Divider for PTA (refresh timer) configuration is based on an
* example SDRAM configuration (64 MBit, one bank). The adjustment to
* the number of chip selects (NCS) and the actually needed refresh
* rate is done by setting MPTPR.
*
* PTA is calculated from
* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
*
* gclk CPU clock (not bus clock!)
* Trefresh Refresh cycle * 4 (four word bursts used)
*
* 4096 Rows from SDRAM example configuration
* 1000 factor s -> ms
* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
* 4 Number of refresh cycles per period
* 64 Refresh cycle in ms per number of rows
* --------------------------------------------
* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
*
* 50 MHz => 50.000.000 / Divider = 98
* 66 Mhz => 66.000.000 / Divider = 129
* 80 Mhz => 80.000.000 / Divider = 156
*/
/* periodic timer for refresh */
#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
#define CFG_MAMR_PTA 98
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
/*
* For 16 MBit, refresh rates could be 31.3 us
* (= 64 ms / 2K = 125 / quad bursts).
* For a simpler initialization, 15.6 us is used instead.
*
* #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
* #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
*/
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
......
......@@ -310,7 +310,6 @@ void start_armboot (void)
if (getenv ("ethaddr")) {
smc_set_mac_addr(gd->bd->bi_enetaddr);
}
eth_init(gd->bd);
#endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */
/* Initialize from environment */
......
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