Commit 5c952cf0 authored by wdenk's avatar wdenk

Patches by Scott McNutt, 24 Aug 2004:

- Add support for Altera Nios-II processors.
- Add support for Psyent PCI-5441 board.
- Add support for Psyent PK1C20 board.
parent 03f5c550
......@@ -2,6 +2,11 @@
Changes since U-Boot 1.1.1:
======================================================================
* Patches by Scott McNutt, 24 Aug 2004:
- Add support for Altera Nios-II processors.
- Add support for Psyent PCI-5441 board.
- Add support for Psyent PK1C20 board.
* Patches by Jon Loeliger, 24 Aug 2004:
- Add support for the MPC8541 and MPC8555 CDS boards
- Cleanup eth?addr handling: make dependent on CONFIG_ETH?ADDR
......
......@@ -286,7 +286,10 @@ D: Support for Samsung ARM920T SMDK2410 eval board
N: Scott McNutt
E: smcnutt@psyent.com
D: Support for Altera Nios-32 CPU, for Nios Cyclone Development Kit (DK-1C20)
D: Support for Altera Nios-32 CPU
D: Support for Altera Nios-II CPU
D: Support for Nios Cyclone Development Kit (DK-1C20)
W: http://www.psyent.com
N: Rolf Offermanns
E: rof@sysgo.de
......
......@@ -430,6 +430,18 @@ Scott McNutt <smcnutt@psyent.com>
DK1C20 Nios-32
#########################################################################
# Nios-II Systems: #
# #
# Maintainer Name, Email Address #
# Board CPU #
#########################################################################
Scott McNutt <smcnutt@psyent.com>
PCI5441 Nios-II
PK1C20 Nios-II
#########################################################################
# MicroBlaze Systems: #
# #
......
......@@ -194,6 +194,12 @@ LIST_nios=" \
DK1S10 DK1S10_standard_32 DK1S10_mtx_ldk_20 \
"
#########################################################################
## Nios-II Systems
#########################################################################
LIST_nios2="PCI5441 PK1C20"
#########################################################################
## MicroBlaze Systems
#########################################################################
......@@ -226,7 +232,7 @@ do
arm|SA|ARM7|ARM9|pxa|ixp| \
microblaze| \
mips| \
nios| \
nios|nios2| \
x86|I486)
for target in `eval echo '$LIST_'${arg}`
do
......
......@@ -72,6 +72,9 @@ endif
ifeq ($(ARCH),nios)
CROSS_COMPILE = nios-elf-
endif
ifeq ($(ARCH),nios2)
CROSS_COMPILE = nios2-elf-
endif
ifeq ($(ARCH),m68k)
CROSS_COMPILE = m68k-elf-
endif
......@@ -1477,6 +1480,15 @@ ADNPESC1_config: unconfig
}
@./mkconfig -a ADNPESC1 nios nios adnpesc1 ssv
#########################################################################
## Nios-II
#########################################################################
PK1C20_config : unconfig
@./mkconfig PK1C20 nios2 nios2 pk1c20 psyent
PCI5441_config : unconfig
@./mkconfig PCI5441 nios2 nios2 pci5441 psyent
#========================================================================
# MicroBlaze
......
......@@ -141,6 +141,7 @@ Directory Hierarchy:
- mpc8260 Files specific to Motorola MPC8260 CPUs
- mpc85xx Files specific to Motorola MPC85xx CPUs
- nios Files specific to Altera NIOS CPUs
- nios2 Files specific to Altera Nios-II CPUs
- ppc4xx Files specific to IBM PowerPC 4xx CPUs
- pxa Files specific to Intel XScale PXA CPUs
- s3c44b0 Files specific to Samsung S3C44B0 CPUs
......@@ -246,6 +247,10 @@ The following options need to be configured:
----------------------
CONFIG_MICROBLAZE
Nios-2 based CPUs:
----------------------
CONFIG_NIOS2
- Board Type: Define exactly one of
......@@ -306,6 +311,11 @@ The following options need to be configured:
CONFIG_SUZAKU
Nios-2 based boards:
------------------------
CONFIG_PCI5441 CONFIG_PK1C20
- CPU Module Type: (if CONFIG_COGENT is defined)
Define exactly one of
......
......@@ -22,7 +22,6 @@
* MA 02111-1307 USA
*/
#include <common.h>
#include <pci.h>
#include <asm/processor.h>
......@@ -41,65 +40,55 @@ extern long int spd_sdram(void);
void local_bus_init(void);
void sdram_init(void);
int
board_early_init_f(void)
int board_early_init_f (void)
{
return 0;
return 0;
}
int
checkboard(void)
int checkboard (void)
{
volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
/* PCI slot in USER bits CSR[6:7] by convention. */
uint pci_slot = get_pci_slot();
uint pci_dual = get_pci_dual(); /* PCI DUAL in CM_PCI[3] */
uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
uint pci1_speed = get_clock_freq(); /* PCI PSPEED in [4:5] */
uint cpu_board_rev = get_cpu_board_revision();
printf("Board: CDS Version 0x%02x, PCI Slot %d\n",
get_board_version(),
pci_slot);
printf("CPU Board Revision %d.%d (0x%04x)\n",
MPC85XX_CPU_BOARD_MAJOR(cpu_board_rev),
MPC85XX_CPU_BOARD_MINOR(cpu_board_rev),
cpu_board_rev);
printf(" PCI1: %d bit, %s MHz, %s\n",
(pci1_32) ? 32 : 64,
(pci1_speed == 33000000) ? "33" :
(pci1_speed == 66000000) ? "66" : "unknown",
pci1_clk_sel ? "sync" : "async"
);
if (pci_dual) {
printf(" PCI2: 32 bit, 66 MHz, %s\n",
pci2_clk_sel ? "sync" : "async"
);
} else {
printf(" PCI2: disabled\n");
}
/*
* Initialize local bus.
*/
local_bus_init();
return 0;
}
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
/* PCI slot in USER bits CSR[6:7] by convention. */
uint pci_slot = get_pci_slot ();
uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
uint cpu_board_rev = get_cpu_board_revision ();
printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
get_board_version (), pci_slot);
printf ("CPU Board Revision %d.%d (0x%04x)\n",
MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
printf (" PCI1: %d bit, %s MHz, %s\n",
(pci1_32) ? 32 : 64,
(pci1_speed == 33000000) ? "33" :
(pci1_speed == 66000000) ? "66" : "unknown",
pci1_clk_sel ? "sync" : "async");
if (pci_dual) {
printf (" PCI2: 32 bit, 66 MHz, %s\n",
pci2_clk_sel ? "sync" : "async");
} else {
printf (" PCI2: disabled\n");
}
/*
* Initialize local bus.
*/
local_bus_init ();
return 0;
}
long int
initdram(int board_type)
......@@ -125,18 +114,14 @@ initdram(int board_type)
udelay(200);
}
#endif
dram_size = spd_sdram();
#if defined(CONFIG_DDR_ECC)
/*
* Initialize and enable DDR ECC.
*/
ddr_enable_ecc(dram_size);
#endif
/*
* SDRAM Initialization
*/
......@@ -146,11 +131,9 @@ initdram(int board_type)
return dram_size;
}
/*
* Initialize Local Bus
*/
void
local_bus_init(void)
{
......@@ -196,11 +179,9 @@ local_bus_init(void)
}
}
/*
* Initialize SDRAM memory on the Local Bus.
*/
void
sdram_init(void)
{
......@@ -292,7 +273,6 @@ sdram_init(void)
#endif /* enable SDRAM init */
}
#if defined(CFG_DRAM_TEST)
int
testdram(void)
......@@ -332,8 +312,6 @@ testdram(void)
}
#endif
#if defined(CONFIG_PCI)
/*
......@@ -352,7 +330,6 @@ static struct pci_config_table pci_mpc85xxcds_config_table[] = {
};
#endif
static struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
config_table: pci_mpc85xxcds_config_table,
......@@ -361,7 +338,6 @@ static struct pci_controller hose = {
#endif /* CONFIG_PCI */
void
pci_init_board(void)
{
......
......@@ -20,7 +20,6 @@
* MA 02111-1307 USA
*/
#include <common.h>
#include <pci.h>
#include <asm/processor.h>
......@@ -39,65 +38,55 @@ extern long int spd_sdram(void);
void local_bus_init(void);
void sdram_init(void);
int
board_early_init_f(void)
int board_early_init_f (void)
{
return 0;
return 0;
}
int
checkboard(void)
int checkboard (void)
{
volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
/* PCI slot in USER bits CSR[6:7] by convention. */
uint pci_slot = get_pci_slot();
uint pci_dual = get_pci_dual(); /* PCI DUAL in CM_PCI[3] */
uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
uint pci1_speed = get_clock_freq(); /* PCI PSPEED in [4:5] */
uint cpu_board_rev = get_cpu_board_revision();
printf("Board: CDS Version 0x%02x, PCI Slot %d\n",
get_board_version(),
pci_slot);
printf("CPU Board Revision %d.%d (0x%04x)\n",
MPC85XX_CPU_BOARD_MAJOR(cpu_board_rev),
MPC85XX_CPU_BOARD_MINOR(cpu_board_rev),
cpu_board_rev);
printf(" PCI1: %d bit, %s MHz, %s\n",
(pci1_32) ? 32 : 64,
(pci1_speed == 33000000) ? "33" :
(pci1_speed == 66000000) ? "66" : "unknown",
pci1_clk_sel ? "sync" : "async"
);
if (pci_dual) {
printf(" PCI2: 32 bit, 66 MHz, %s\n",
pci2_clk_sel ? "sync" : "async"
);
} else {
printf(" PCI2: disabled\n");
}
/*
* Initialize local bus.
*/
local_bus_init();
return 0;
}
volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
/* PCI slot in USER bits CSR[6:7] by convention. */
uint pci_slot = get_pci_slot ();
uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
uint pci1_32 = gur->pordevsr & 0x10000; /* PORDEVSR[15] */
uint pci1_clk_sel = gur->porpllsr & 0x8000; /* PORPLLSR[16] */
uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
uint pci1_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
uint cpu_board_rev = get_cpu_board_revision ();
printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
get_board_version (), pci_slot);
printf ("CPU Board Revision %d.%d (0x%04x)\n",
MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
printf (" PCI1: %d bit, %s MHz, %s\n",
(pci1_32) ? 32 : 64,
(pci1_speed == 33000000) ? "33" :
(pci1_speed == 66000000) ? "66" : "unknown",
pci1_clk_sel ? "sync" : "async");
if (pci_dual) {
printf (" PCI2: 32 bit, 66 MHz, %s\n",
pci2_clk_sel ? "sync" : "async");
} else {
printf (" PCI2: disabled\n");
}
/*
* Initialize local bus.
*/
local_bus_init ();
return 0;
}
long int
initdram(int board_type)
......@@ -123,18 +112,14 @@ initdram(int board_type)
udelay(200);
}
#endif
dram_size = spd_sdram();
#if defined(CONFIG_DDR_ECC)
/*
* Initialize and enable DDR ECC.
*/
ddr_enable_ecc(dram_size);
#endif
/*
* SDRAM Initialization
*/
......@@ -144,11 +129,9 @@ initdram(int board_type)
return dram_size;
}
/*
* Initialize Local Bus
*/
void
local_bus_init(void)
{
......@@ -194,11 +177,9 @@ local_bus_init(void)
}
}
/*
* Initialize SDRAM memory on the Local Bus.
*/
void
sdram_init(void)
{
......@@ -227,7 +208,6 @@ sdram_init(void)
lbc->lbcr = CFG_LBC_LBCR;
asm("msync");
lbc->lsrt = CFG_LBC_LSRT;
lbc->mrtpr = CFG_LBC_MRTPR;
asm("msync");
......@@ -290,7 +270,6 @@ sdram_init(void)
#endif /* enable SDRAM init */
}
#if defined(CFG_DRAM_TEST)
int
testdram(void)
......@@ -330,8 +309,6 @@ testdram(void)
}
#endif
#if defined(CONFIG_PCI)
/*
......@@ -350,7 +327,6 @@ static struct pci_config_table pci_mpc85xxcds_config_table[] = {
};
#endif
static struct pci_controller hose = {
#ifndef CONFIG_PCI_PNP
config_table: pci_mpc85xxcds_config_table,
......@@ -359,7 +335,6 @@ static struct pci_controller hose = {
#endif /* CONFIG_PCI */
void
pci_init_board(void)
{
......
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if defined(CONFIG_NIOS)
#include <nios.h>
#else
#include <nios2.h>
#endif
#define SECTSZ (64 * 1024)
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
/*----------------------------------------------------------------------*/
unsigned long flash_init (void)
{
int i;
unsigned long addr;
flash_info_t *fli = &flash_info[0];
fli->size = CFG_FLASH_SIZE;
fli->sector_count = CFG_MAX_FLASH_SECT;
fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
addr = CFG_FLASH_BASE;
for (i = 0; i < fli->sector_count; ++i) {
fli->start[i] = addr;
addr += SECTSZ;
fli->protect[i] = 1;
}
return (CFG_FLASH_SIZE);
}
/*--------------------------------------------------------------------*/
void flash_print_info (flash_info_t * info)
{
int i, k;
unsigned long size;
int erased;
volatile unsigned char *flash;
printf (" Size: %ld KB in %d Sectors\n",
info->size >> 10, info->sector_count);
printf (" Sector Start Addresses:");
for (i = 0; i < info->sector_count; ++i) {
/* Check if whole sector is erased */
if (i != (info->sector_count - 1))
size = info->start[i + 1] - info->start[i];
else
size = info->start[0] + info->size - info->start[i];
erased = 1;
flash = (volatile unsigned char *) CACHE_BYPASS(info->start[i]);
for (k = 0; k < size; k++) {
if (*flash++ != 0xff) {
erased = 0;
break;
}
}
/* Print the info */
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s%s",
CACHE_NO_BYPASS(info->start[i]),
erased ? " E" : " ",
info->protect[i] ? "RO " : " ");
}
printf ("\n");
}
/*-------------------------------------------------------------------*/
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)
CACHE_BYPASS(info->start[0]);
volatile CFG_FLASH_WORD_SIZE *addr2;
int prot, sect;
ulong start;
/* Some sanity checking */
if ((s_first < 0) || (s_first > s_last)) {
printf ("- no sectors to erase\n");
return 1;
}
prot = 0;