Commit 9455b7f3 authored by wdenk's avatar wdenk

Fix CFG_HZ problems on AT91RM9200 systems

[Remember: CFG_HZ should be 1000 on ALL systems!]
parent e1599e83
......@@ -2,6 +2,9 @@
Changes since U-Boot 1.1.1:
======================================================================
* Fix CFG_HZ problems on AT91RM9200 systems
[Remember: CFG_HZ should be 1000 on ALL systems!]
* Patch by Gridish Shlomi, 30 Aug 2004:
- Add support to revA version of PQ27 and PQ27E.
- Reverted MPC8260ADS baudrate back to original 115200
......
......@@ -37,8 +37,8 @@
extern void reset_cpu(ulong addr);
/* we always count down the max. */
#define TIMER_LOAD_VAL 0xffff
/* the number of clocks per CFG_HZ */
#define TIMER_LOAD_VAL (CFG_HZ_CLOCK/CFG_HZ)
/* macro to read the 16 bit timer */
#define READ_TIMER (tmr->TC_CV & 0x0000ffff)
......@@ -165,11 +165,13 @@ int interrupt_init (void)
*AT91C_TCB0_BCR = 0;
*AT91C_TCB0_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE;
tmr->TC_CCR = AT91C_TC_CLKDIS;
tmr->TC_CMR = AT91C_TC_TIMER_DIV1_CLOCK; /* set to MCLK/2 */
#define AT91C_TC_CMR_CPCTRG (1 << 14)
/* set to MCLK/2 and restart the timer when the vlaue in TC_RC is reached */
tmr->TC_CMR = AT91C_TC_TIMER_DIV1_CLOCK | AT91C_TC_CMR_CPCTRG;
tmr->TC_IDR = ~0ul;
tmr->TC_RC = TIMER_LOAD_VAL;
lastinc = TIMER_LOAD_VAL;
lastinc = 0;
tmr->TC_CCR = AT91C_TC_SWTRG | AT91C_TC_CLKEN;
timestamp = 0;
......@@ -207,7 +209,7 @@ void reset_timer_masked (void)
timestamp = 0;
}
ulong get_timer_masked (void)
ulong get_timer_raw (void)
{
ulong now = READ_TIMER;
......@@ -223,17 +225,27 @@ ulong get_timer_masked (void)
return timestamp;
}
ulong get_timer_masked (void)
{
return get_timer_raw()/TIMER_LOAD_VAL;
}
void udelay_masked (unsigned long usec)
{
ulong tmo;
#if 0 /* doesn't work for usec < 1000 */
tmo = usec / 1000;
tmo *= CFG_HZ;
tmo *= CFG_HZ_CLOCK;
#else
tmo = CFG_HZ_CLOCK / 1000;
tmo *= usec;
#endif
tmo /= 1000;
reset_timer_masked ();
while (get_timer_masked () < tmo)
while (get_timer_raw () < tmo)
/*NOP*/;
}
......
......@@ -182,7 +182,8 @@ struct bd_info_ext {
};
#endif
#define CFG_HZ AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
#define CFG_HZ 1000
#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
/* AT91C_TC_TIMER_DIV1_CLOCK */
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
......
......@@ -71,7 +71,7 @@
#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
#define CONFIG_HARD_I2C
#undef CONFIG_HARD_I2C
#ifdef CONFIG_HARD_I2C
#define CFG_I2C_SPEED 0 /* not used */
......@@ -90,6 +90,7 @@
#define CONFIG_COMMANDS \
((CONFIG_CMD_DFL | \
CFG_CMD_I2C | \
CFG_CMD_DATE | \
CFG_CMD_EEPROM | \
CFG_CMD_DHCP ) & \
~(CFG_CMD_BDI | \
......@@ -213,7 +214,8 @@ struct bd_info_ext {
};
#endif
#define CFG_HZ AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
#define CFG_HZ 1000
#define CFG_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
/* AT91C_TC_TIMER_DIV1_CLOCK */
#define CONFIG_STACKSIZE (32*1024) /* regular stack */
......
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