Commit a06752e3 authored by wdenk's avatar wdenk

* Patch by Sean Chang, 9 Aug 2004:

  - Added I2C support for ML300.
  - Added support for ML300 to read out its environment information
    stored on the EEPROM.
  - Added support to use board specific parameters as part of
    U-Boot's environment information.
  - Updated MLD files to support configuration for new features
    above.

* Patches by Travis Sawyer, 5 Aug 2004:
  - Remove incorrect bridge settings for eth group 6
  - Add call to setup bridge in ppc_440x_eth_initialize
  - Fix ppc_440x_eth_init to reset the phy only if its the
    first time through, otherwise, just check the phy for the
    autonegotiated speed/duplex.  This allows the use of netconsole
  - only print the speed/duplex the first time the phy is reset.
parent da93ed81
......@@ -2,6 +2,23 @@
Changes since U-Boot 1.1.1:
======================================================================
* Patch by Sean Chang, 9 Aug 2004:
- Added I2C support for ML300.
- Added support for ML300 to read out its environment information
stored on the EEPROM.
- Added support to use board specific parameters as part of
U-Boot's environment information.
- Updated MLD files to support configuration for new features
above.
* Patches by Travis Sawyer, 5 Aug 2004:
- Remove incorrect bridge settings for eth group 6
- Add call to setup bridge in ppc_440x_eth_initialize
- Fix ppc_440x_eth_init to reset the phy only if its the
first time through, otherwise, just check the phy for the
autonegotiated speed/duplex. This allows the use of netconsole
- only print the speed/duplex the first time the phy is reset.
* Patch by Shlomo Kut, 29 Mar 2004:
Add support for MKS Instruments "Quantum" board
......
/* $Id: xipif_v1_23_b.c,v 1.1 2002/03/18 23:24:52 linnj Exp $ */
/******************************************************************************
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/******************************************************************************
*
* FILENAME:
*
* xipif.c
*
* DESCRIPTION:
*
* This file contains the implementation of the XIpIf component. The
* XIpIf component encapsulates the IPIF, which is the standard interface
* that IP must adhere to when connecting to a bus. The purpose of this
* component is to encapsulate the IPIF processing such that maintainability
* is increased. This component does not provide a lot of abstraction from
* from the details of the IPIF as it is considered a building block for
* device drivers. A device driver designer must be familiar with the
* details of the IPIF hardware to use this component.
*
* The IPIF hardware provides a building block for all hardware devices such
* that each device does not need to reimplement these building blocks. The
* IPIF contains other building blocks, such as FIFOs and DMA channels, which
* are also common to many devices. These blocks are implemented as separate
* hardware blocks and instantiated within the IPIF. The primary hardware of
* the IPIF which is implemented by this software component is the interrupt
* architecture. Since there are many blocks of a device which may generate
* interrupts, all the interrupt processing is contained in the common part
* of the device, the IPIF. This interrupt processing is for the device level
* only and does not include any processing for the interrupt controller.
*
* A device is a mechanism such as an Ethernet MAC. The device is made
* up of several parts which include an IPIF and the IP. The IPIF contains most
* of the device infrastructure which is common to all devices, such as
* interrupt processing, DMA channels, and FIFOs. The infrastructure may also
* be referred to as IPIF internal blocks since they are part of the IPIF and
* are separate blocks that can be selected based upon the needs of the device.
* The IP of the device is the logic that is unique to the device and interfaces
* to the IPIF of the device.
*
* In general, there are two levels of registers within the IPIF. The first
* level, referred to as the device level, contains registers which are for the
* entire device. The second level, referred to as the IP level, contains
* registers which are specific to the IP of the device. The two levels of
* registers are designed to be hierarchical such that the device level is
* is a more general register set above the more specific registers of the IP.
* The IP level of registers provides functionality which is typically common
* across all devices and allows IP designers to focus on the unique aspects
* of the IP.
*
* The interrupt registers of the IPIF are parameterizable such that the only
* the number of bits necessary for the device are implemented. The functions
* of this component do not attempt to validate that the passed in arguments are
* valid based upon the number of implemented bits. This is necessary to
* maintain the level of performance required for the common components. Bits
* of the registers are assigned starting at the least significant bit of the
* registers.
*
* Critical Sections
*
* It is the responsibility of the device driver designer to use critical
* sections as necessary when calling functions of the IPIF. This component
* does not use critical sections and it does access registers using
* read-modify-write operations. Calls to IPIF functions from a main thread
* and from an interrupt context could produce unpredictable behavior such that
* the caller must provide the appropriate critical sections.
*
* Mutual Exclusion
*
* The functions of the IPIF are not thread safe such that the caller of all
* functions is responsible for ensuring mutual exclusion for an IPIF. Mutual
* exclusion across multiple IPIF components is not necessary.
*
* NOTES:
*
* None.
*
* MODIFICATION HISTORY:
*
* Ver Who Date Changes
* ----- ---- -------- -----------------------------------------------
* 1.23b jhl 02/27/01 Repartioned to reduce size
*
******************************************************************************/
/***************************** Include Files *********************************/
#include "xipif_v1_23_b.h"
#include "xio.h"
/************************** Constant Definitions *****************************/
/* the following constant is used to generate bit masks for register testing
* in the self test functions, it defines the starting bit mask that is to be
* shifted from the LSB to MSB in creating a register test mask
*/
#define XIIF_V123B_FIRST_BIT_MASK 1UL
/**************************** Type Definitions *******************************/
/***************** Macros (Inline Functions) Definitions *********************/
/************************** Variable Definitions *****************************/
/************************** Function Prototypes ******************************/
static XStatus IpIntrSelfTest(u32 RegBaseAddress, u32 IpRegistersWidth);
/******************************************************************************
*
* FUNCTION:
*
* XIpIf_SelfTest
*
* DESCRIPTION:
*
* This function performs a self test on the specified IPIF component. Many
* of the registers in the IPIF are tested to ensure proper operation. This
* function is destructive because the IPIF is reset at the start of the test
* and at the end of the test to ensure predictable results. The IPIF reset
* also resets the entire device that uses the IPIF. This function exits with
* all interrupts for the device disabled.
*
* ARGUMENTS:
*
* InstancePtr points to the XIpIf to operate on.
*
* DeviceRegistersWidth contains the number of bits in the device interrupt
* registers. The hardware is parameterizable such that only the number of bits
* necessary to support a device are implemented. This value must be between 0
* and 32 with 0 indicating there are no device interrupt registers used.
*
* IpRegistersWidth contains the number of bits in the IP interrupt registers
* of the device. The hardware is parameterizable such that only the number of
* bits necessary to support a device are implemented. This value must be
* between 0 and 32 with 0 indicating there are no IP interrupt registers used.
*
* RETURN VALUE:
*
* A value of XST_SUCCESS indicates the test was successful with no errors.
* Any one of the following error values may also be returned.
*
* XST_IPIF_RESET_REGISTER_ERROR The value of a register at reset was
* not valid
* XST_IPIF_IP_STATUS_ERROR A write to the IP interrupt status
* register did not read back correctly
* XST_IPIF_IP_ACK_ERROR One or more bits in the IP interrupt
* status register did not reset when acked
* XST_IPIF_IP_ENABLE_ERROR The IP interrupt enable register
* did not read back correctly based upon
* what was written to it
*
* NOTES:
*
* None.
*
******************************************************************************/
/* the following constant defines the maximum number of bits which may be
* used in the registers at the device and IP levels, this is based upon the
* number of bits available in the registers
*/
#define XIIF_V123B_MAX_REG_BIT_COUNT 32
XStatus
XIpIfV123b_SelfTest(u32 RegBaseAddress, u8 IpRegistersWidth)
{
XStatus Status;
/* assert to verify arguments are valid */
XASSERT_NONVOID(IpRegistersWidth <= XIIF_V123B_MAX_REG_BIT_COUNT);
/* reset the IPIF such that it's in a known state before the test
* and interrupts are globally disabled
*/
XIIF_V123B_RESET(RegBaseAddress);
/* perform the self test on the IP interrupt registers, if
* it is not successful exit with the status
*/
Status = IpIntrSelfTest(RegBaseAddress, IpRegistersWidth);
if (Status != XST_SUCCESS) {
return Status;
}
/* reset the IPIF such that it's in a known state before exiting test */
XIIF_V123B_RESET(RegBaseAddress);
/* reaching this point means there were no errors, return success */
return XST_SUCCESS;
}
/******************************************************************************
*
* FUNCTION:
*
* IpIntrSelfTest
*
* DESCRIPTION:
*
* Perform a self test on the IP interrupt registers of the IPIF. This
* function modifies registers of the IPIF such that they are not guaranteed
* to be in the same state when it returns. Any bits in the IP interrupt
* status register which are set are assumed to be set by default after a reset
* and are not tested in the test.
*
* ARGUMENTS:
*
* InstancePtr points to the XIpIf to operate on.
*
* IpRegistersWidth contains the number of bits in the IP interrupt registers
* of the device. The hardware is parameterizable such that only the number of
* bits necessary to support a device are implemented. This value must be
* between 0 and 32 with 0 indicating there are no IP interrupt registers used.
*
* RETURN VALUE:
*
* A status indicating XST_SUCCESS if the test was successful. Otherwise, one
* of the following values is returned.
*
* XST_IPIF_RESET_REGISTER_ERROR The value of a register at reset was
* not valid
* XST_IPIF_IP_STATUS_ERROR A write to the IP interrupt status
* register did not read back correctly
* XST_IPIF_IP_ACK_ERROR One or more bits in the IP status
* register did not reset when acked
* XST_IPIF_IP_ENABLE_ERROR The IP interrupt enable register
* did not read back correctly based upon
* what was written to it
* NOTES:
*
* None.
*
******************************************************************************/
static XStatus
IpIntrSelfTest(u32 RegBaseAddress, u32 IpRegistersWidth)
{
/* ensure that the IP interrupt interrupt enable register is zero
* as it should be at reset, the interrupt status is dependent upon the
* IP such that it's reset value is not known
*/
if (XIIF_V123B_READ_IIER(RegBaseAddress) != 0) {
return XST_IPIF_RESET_REGISTER_ERROR;
}
/* if there are any used IP interrupts, then test all of the interrupt
* bits in all testable registers
*/
if (IpRegistersWidth > 0) {
u32 BitCount;
u32 IpInterruptMask = XIIF_V123B_FIRST_BIT_MASK;
u32 Mask = XIIF_V123B_FIRST_BIT_MASK; /* bits assigned MSB to LSB */
u32 InterruptStatus;
/* generate the register masks to be used for IP register tests, the
* number of bits supported by the hardware is parameterizable such
* that only that number of bits are implemented in the registers, the
* bits are allocated starting at the MSB of the registers
*/
for (BitCount = 1; BitCount < IpRegistersWidth; BitCount++) {
Mask = Mask << 1;
IpInterruptMask |= Mask;
}
/* get the current IP interrupt status register contents, any bits
* already set must default to 1 at reset in the device and these
* bits can't be tested in the following test, remove these bits from
* the mask that was generated for the test
*/
InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
IpInterruptMask &= ~InterruptStatus;
/* set the bits in the device status register and verify them by reading
* the register again, all bits of the register are latched
*/
XIIF_V123B_WRITE_IISR(RegBaseAddress, IpInterruptMask);
InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
if ((InterruptStatus & IpInterruptMask) != IpInterruptMask)
{
return XST_IPIF_IP_STATUS_ERROR;
}
/* test to ensure that the bits set in the IP interrupt status register
* can be cleared by acknowledging them in the IP interrupt status
* register then read it again and verify it was cleared
*/
XIIF_V123B_WRITE_IISR(RegBaseAddress, IpInterruptMask);
InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
if ((InterruptStatus & IpInterruptMask) != 0) {
return XST_IPIF_IP_ACK_ERROR;
}
/* set the IP interrupt enable set register and then read the IP
* interrupt enable register and verify the interrupts were enabled
*/
XIIF_V123B_WRITE_IIER(RegBaseAddress, IpInterruptMask);
if (XIIF_V123B_READ_IIER(RegBaseAddress) != IpInterruptMask) {
return XST_IPIF_IP_ENABLE_ERROR;
}
/* clear the IP interrupt enable register and then read the
* IP interrupt enable register and verify the interrupts were disabled
*/
XIIF_V123B_WRITE_IIER(RegBaseAddress, 0);
if (XIIF_V123B_READ_IIER(RegBaseAddress) != 0) {
return XST_IPIF_IP_ENABLE_ERROR;
}
}
return XST_SUCCESS;
}
/* $Id: xipif_v1_23_b.h,v 1.1 2002/03/18 23:24:52 linnj Exp $ */
/******************************************************************************
*
* Author: Xilinx, Inc.
*
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
* COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
* ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
* XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
* FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
* ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
* XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
* THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
* WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
* CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE.
*
*
* Xilinx hardware products are not intended for use in life support
* appliances, devices, or systems. Use in such applications is
* expressly prohibited.
*
*
* (c) Copyright 2002-2004 Xilinx Inc.
* All rights reserved.
*
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE.
*
* (c) Copyright 2002 Xilinx Inc.
* All rights reserved.
*
******************************************************************************/
/******************************************************************************
......@@ -575,7 +558,7 @@
*
* RETURN VALUE:
*
* TRUE if interrupts are enabled for the IPIF, FALSE otherwise.
* XTRUE if interrupts are enabled for the IPIF, XFALSE otherwise.
*
* NOTES:
*
......
......@@ -19,22 +19,23 @@
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
CFLAGS += -I../ml300 -I../common -I../xilinx_enet
CFLAGS += -I../ml300 -I../common -I../xilinx_enet -I../xilinx_iic
LIB = lib$(BOARD).a
OBJS = $(BOARD).o serial.o \
../xilinx_enet/emac_adapter.o ../xilinx_enet/xemac.o \
OBJS = $(BOARD).o \
serial.o \
../xilinx_enet/emac_adapter.o ../xilinx_enet/xemac.o \
../xilinx_enet/xemac_options.o ../xilinx_enet/xemac_polled.o \
../xilinx_enet/xemac_intr.o ../xilinx_enet/xemac_g.o \
../xilinx_enet/xemac_intr_dma.o \
../xilinx_enet/xemac_intr_dma.o ../xilinx_iic/iic_adapter.o \
../xilinx_iic/xiic_l.o ../common/xipif_v1_23_b.o \
../common/xbasic_types.o ../common/xdma_channel.o \
../common/xdma_channel_sg.o ../common/xpacket_fifo_v1_00_b.o \
../common/xversion.o
../common/xversion.o \
SOBJS = init.o
......
......@@ -42,6 +42,10 @@
#include <asm/processor.h>
#include "xparameters.h"
#ifdef CFG_ENV_IS_IN_EEPROM
extern void convert_env(void);
#endif
int
board_pre_init(void)
{
......@@ -51,22 +55,25 @@ board_pre_init(void)
int
checkboard(void)
{
unsigned char *s = getenv("serial#");
unsigned char *e;
uchar tmp[64]; /* long enough for environment variables */
uchar *s, *e;
int i = getenv_r("L", tmp, sizeof (tmp));
if (!s || strncmp(s, "ML300", 9)) {
if (i < 0) {
printf("### No HW ID - assuming ML300");
} else {
for (e = s; *e; ++e) {
for (e = tmp; *e; ++e) {
if (*e == ' ')
break;
}
for (; s < e; ++s) {
printf("### Board Serial# is ");
for (s = tmp; s < e; ++s) {
putc(*s);
}
}
}
putc('\n');
return (0);
......@@ -107,3 +114,15 @@ get_PCI_freq(void)
val = sys_info.freqPCI;
return val;
}
#ifdef CONFIG_MISC_INIT_R
int
misc_init_r()
{
/* convert env name and value to u-boot standard */
convert_env();
return 0;
}
#endif
#!/bin/bash
if[$
# -ne 1 ]
then echo "usage: Ltypes filename" > &2 exit 2 fi FILE = "$1"
if [ $# -ne 1 ]
then
echo "usage: Ltypes filename" >&2
exit 2
fi
FILE="$1"
#TMPFILE='mktemp "${FILE}.XXXXXX"' || exit 1
TMPFILE = $ {
FILE}
TMPFILE=${FILE}.`date "+%s"`
touch $TMPFILE || exit 1
. ` date "+%s" ` touch $TMPFILE || exit 1
# Change all the Xilinx types to Linux types and put the result into a temp file
sed
- e 's/\bXTRUE\b/TRUE/g'
- e 's/\bXFALSE\b/FALSE/g'
- e 's/\bXNULL\b/NULL/g'
- e 's/<asm/delay.h>/<asm\/delay.h>/g'
- e 's/\bXENV_USLEEP\b/udelay/g'
- e 's/\bXuint8\b/u8/g'
- e 's/\bXuint16\b/u16/g'
- e 's/\bXuint32\b/u32/g'
- e 's/\bXint8\b/s8/g'
- e 's/\bXint16\b/s16/g'
- e 's/\bXint32\b/s32/g' - e 's/\bXboolean\b/u32/g' "${FILE}" > "${TMPFILE}"
sed \
-e 's/\bXTRUE\b/TRUE/g' \
-e 's/\bXFALSE\b/FALSE/g' \
-e 's/\bXNULL\b/NULL/g' \
-e 's/"xenv.h"/<asm\/delay.h>/g' \
-e 's/\bXENV_USLEEP\b/udelay/g' \
-e 's/\bXuint8\b/u8/g' \
-e 's/\bXuint16\b/u16/g' \
-e 's/\bXuint32\b/u32/g' \
-e 's/\bXint8\b/s8/g' \
-e 's/\bXint16\b/s16/g' \
-e 's/\bXint32\b/s32/g' \
-e 's/\bXboolean\b/u32/g' \
"${FILE}" > "${TMPFILE}"
# Overlay the original file with the temp file
mv "${TMPFILE}" "${FILE}"
mv "${TMPFILE}" "${FILE}"
# Are we doing xbasic_types.h?
if["${FILE##*/}" = xbasic_types.h]
then
# Remember as you're reading this that we've already gone through the prior
# sed script. We need to do some other things to xbasic_types.h:
# 1) Add ifndefs around TRUE and FALSE defines
# 2) Remove definition of NULL as NULL
# 3) Replace most of the primitive types section with a #include
sed - e '/u32 true/,/#define false/Ic\
if [ "${FILE##*/}" = xbasic_types.h ]
then
# Remember as you're reading this that we've already gone through the prior
# sed script. We need to do some other things to xbasic_types.h:
# 1) Add ifndefs around TRUE and FALSE defines
# 2) Remove definition of NULL as NULL
# 3) Replace most of the primitive types section with a #include
sed \
-e '/u32 true/,/#define false/Ic\
#ifndef TRUE\
#define TRUE 1\
#endif\
#ifndef FALSE\
#define FALSE 0\
#endif' - e '/#define[[:space:]][[:space:]]*NULL[[:space:]][[:space:]]*NULL/d' - e '/typedef[[:space:]][[:space:]]*unsigned[[:space:]][[:space:]]*char[[:space:]][[:space:]]*u8/,/typedef[[:space:]][[:space:]]*unsigned[[:space:]][[:space:]]*long[[:space:]][[:space:]]*u32.*boolean/c\
#include <linux/types.h>' "${FILE}" > "${TMPFILE}" mv "${TMPFILE}" "${FILE}" fi
#endif' \
-e '/#define[[:space:]][[:space:]]*NULL[[:space:]][[:space:]]*NULL/d' \
-e '/typedef[[:space:]][[:space:]]*unsigned[[:space:]][[:space:]]*char[[:space:]][[:space:]]*u8/,/typedef[[:space:]][[:space:]]*unsigned[[:space:]][[:space:]]*long[[:space:]][[:space:]]*u32.*boolean/c\
#include <linux/types.h>' \
"${FILE}" > "${TMPFILE}"
mv "${TMPFILE}" "${FILE}"
fi
......@@ -42,7 +42,11 @@ BEGIN ARRAY connected_periphs PROPERTY desc = "Peripherals connected to U-Boot";
PROPERTY size = 0;
PARAM name = periph_name, desc = "Name of Peripheral connected", type = string;
END ARRAY
PARAMETER name = TARGET_DIR, desc =
"Target Directory for U-Boot BSP", type = string;
PARAMETER name = TARGET_DIR, desc = "Target Directory for U-Boot BSP", type = string;
# location of persistent storage in the IIC EEPROM (defaults are set for ML300)
PARAMETER name = IIC_PERSISTENT_BASEADDR, desc = "Start of persistent storage block in the EEPROM address space", type = int, default = 1024;
PARAMETER name = IIC_PERSISTENT_HIGHADDR, desc = "End of persistent storage block in the EEPROM address space", type = int, default = 2047;
PARAMETER name = IIC_PERSISTENT_EEPROMADDR, desc = "Address of the EEPROM on the IIC bus", type = int, default = 0xA0;
END LIBRARY
......@@ -76,12 +76,18 @@ proc generate {libname} {
xredefine_uartns550 $drv "xparameters.h"
} elseif {[string compare -nocase $drvname "emac"] == 0} {
xredefine_emac $drv "xparameters.h"
} elseif {[string compare -nocase $drvname "iic"] == 0} {
xredefine_iic $drv "xparameters.h"
}
}
}
# define core_clock
xredefine_params $libname "xparameters.h" "CORE_CLOCK_FREQ_HZ"
# define the values for the persistent storage in IIC
xredefine_params $libname "xparameters.h" "IIC_PERSISTENT_BASEADDR" "IIC_PERSISTENT_HIGHADDR" "IIC_PERSISTENT_EEPROMADDR"
}