Commit b4757cee authored by wdenk's avatar wdenk
Browse files

Fix flash driver for TRAB board (must use Unlock Bypass Reset command

to exit Unlock Bypass Mode); adjust timings for flash, SRAM and CPLD
parent 5bb226e8
......@@ -2,6 +2,10 @@
Changes since U-Boot 1.0.0:
======================================================================
* Fix flash driver for TRAB board (must use Unlock Bypass Reset
command to exit Unlock Bypass Mode); adjust timings for flash, SRAM
and CPLD
* Use "-fPIC" instead of "-mrelocatable" to prevent problems with
recent tools
......
......@@ -39,7 +39,10 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
#define CMD_PROGRAM 0x00A000A0
#define CMD_UNLOCK_BYPASS 0x00200020
#define CMD_READ_MANF_ID 0x00900090
#define CMD_UNLOCK_BYPASS_RES1 0x00900090
#define CMD_UNLOCK_BYPASS_RES2 0x00000000
#define MEM_FLASH_ADDR (*(volatile u32 *)CFG_FLASH_BASE)
#define MEM_FLASH_ADDR1 (*(volatile u32 *)(CFG_FLASH_BASE + (0x00000555 << 2)))
#define MEM_FLASH_ADDR2 (*(volatile u32 *)(CFG_FLASH_BASE + (0x000002AA << 2)))
......@@ -331,9 +334,6 @@ volatile static int write_word (flash_info_t * info, ulong dest,
#endif
iflag = disable_interrupts ();
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
*addr = CMD_PROGRAM;
*addr = data;
......@@ -402,6 +402,10 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
int l;
int i, rc;
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
MEM_FLASH_ADDR1 = CMD_UNLOCK_BYPASS;
wp = (addr & ~3); /* get lower word aligned address */
/*
......@@ -422,7 +426,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
}
if ((rc = write_word (info, wp, data)) != 0) {
return (rc);
goto Done;
}
wp += 4;
}
......@@ -441,7 +445,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
}
if ((rc = write_word (info, wp, data)) != 0) {
return (rc);
goto Done;
}
src += 4;
wp += 4;
......@@ -449,7 +453,8 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
}
if (cnt == 0) {
return ERR_OK;
rc = ERR_OK;
goto Done;
}
/*
......@@ -464,7 +469,14 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
data = (data >> 8) | (*(uchar *) cp << 24);
}
return write_word (info, wp, data);
rc = write_word (info, wp, data);
Done:
MEM_FLASH_ADDR = CMD_UNLOCK_BYPASS_RES1;
MEM_FLASH_ADDR = CMD_UNLOCK_BYPASS_RES2;
return (rc);
}
/*-----------------------------------------------------------------------
......
......@@ -48,29 +48,29 @@
#define BWSCON 0x14000000
/* Bank0 */
#define B0_Tacs 0x3 /* 4 clk */
#define B0_Tcos 0x3 /* 4 clk */
#define B0_Tacc 0x7 /* 14 clk */
#define B0_Tcoh 0x0 /* 0 clk */
#define B0_Tah 0x0 /* 0 clk */
#define B0_Tacs 0x1 /* 1 clk */
#define B0_Tcos 0x1 /* 1 clk */
#define B0_Tacc 0x5 /* 8 clk */
#define B0_Tcoh 0x1 /* 1 clk */
#define B0_Tah 0x1 /* 1 clk */
#define B0_Tacp 0x0
#define B0_PMC 0x0 /* normal */
/* Bank1 - SRAM */
#define B1_Tacs 0x0 /* 0 clk */
#define B1_Tcos 0x0 /* 0 clk */
#define B1_Tacc 0x7 /* 14 clk */
#define B1_Tcoh 0x0 /* 0 clk */
#define B1_Tah 0x0 /* 0 clk */
#define B1_Tacs 0x1 /* 1 clk */
#define B1_Tcos 0x1 /* 1 clk */
#define B1_Tacc 0x5 /* 8 clk */
#define B1_Tcoh 0x1 /* 1 clk */
#define B1_Tah 0x1 /* 1 clk */
#define B1_Tacp 0x0
#define B1_PMC 0x0 /* normal */
/* Bank2 - CPLD */
#define B2_Tacs 0x0 /* 0 clk */
#define B2_Tcos 0x4 /* 4 clk */
#define B2_Tacc 0x7 /* 14 clk */
#define B2_Tcoh 0x4 /* 4 clk */
#define B2_Tah 0x0 /* 0 clk */
#define B2_Tacs 0x1 /* 1 clk */
#define B2_Tcos 0x1 /* 1 clk */
#define B2_Tacc 0x5 /* 8 clk */
#define B2_Tcoh 0x1 /* 1 clk */
#define B2_Tah 0x1 /* 1 clk */
#define B2_Tacp 0x0
#define B2_PMC 0x0 /* normal */
......
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