Commit cea655a2 authored by wdenk's avatar wdenk

Add support for the second Ethernet interface for the 'PPChameleon' board.

parent a56bd922
......@@ -2,6 +2,9 @@
Changes since U-Boot 1.1.1:
======================================================================
* Add support for the second Ethernet interface for the 'PPChameleon'
board.
* Patch by Dave Peverley, 30 Apr 2004:
Add support for OMAP730 Perseus2 Development board
......
......@@ -86,17 +86,17 @@
#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
( defined(CONFIG_440) && !defined(CONFIG_NET_MULTI))
#if !defined(CONFIG_NET_MULTI) || !defined(CONFIG_405EP)
/* 405GP, 440 with !CONFIG_NET_MULTI. For 440 only EMAC0 is supported */
#define EMAC_NUM_DEV 1
#else
/* 440EP && CONFIG_NET_MULTI */
#define EMAC_NUM_DEV 2
#endif
#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
#define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
#define NUM_TX_BUFF 1
/* AS.HARNOIS
* Use PKTBUFSRX (include/net.h) instead of setting NUM_RX_BUFF again
* These both variables are used to define the same thing!
* #define NUM_RX_BUFF 4
*/
#define NUM_RX_BUFF PKTBUFSRX
/* Ethernet Transmit and Receive Buffers */
/* AS.HARNOIS
* In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
......@@ -105,11 +105,9 @@
#define ENET_MAX_MTU PKTSIZE
#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
static char *txbuf_ptr;
/* define the number of channels implemented */
#define EMAC_RXCHL 1
#define EMAC_TXCHL 1
#define EMAC_RXCHL EMAC_NUM_DEV
#define EMAC_TXCHL EMAC_NUM_DEV
/*-----------------------------------------------------------------------------+
* Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
......@@ -118,92 +116,66 @@ static char *txbuf_ptr;
#define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
#define EMAC_UIC_DEF UIC_ENET
#define EMAC_UIC_DEF1 UIC_ENET1
#define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
/*-----------------------------------------------------------------------------+
* Global variables. TX and RX descriptors and buffers.
*-----------------------------------------------------------------------------*/
static volatile mal_desc_t *tx;
static volatile mal_desc_t *rx;
static mal_desc_t *alloc_tx_buf = NULL;
static mal_desc_t *alloc_rx_buf = NULL;
/* IER globals */
static unsigned long emac_ier;
static unsigned long mal_ier;
/* Statistic Areas */
#define MAX_ERR_LOG 10
struct emac_stats {
int data_len_err;
int rx_frames;
int rx;
int rx_prot_err;
};
static struct stats { /* Statistic Block */
struct emac_stats emac;
int int_err;
short tx_err_log[MAX_ERR_LOG];
short rx_err_log[MAX_ERR_LOG];
} stats;
static int first_init = 0;
static int tx_err_index = 0; /* Transmit Error Index for tx_err_log */
static int rx_err_index = 0; /* Receive Error Index for rx_err_log */
static int rx_slot = 0; /* MAL Receive Slot */
static int rx_i_index = 0; /* Receive Interrupt Queue Index */
static int rx_u_index = 0; /* Receive User Queue Index */
static int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */
static int tx_slot = 0; /* MAL Transmit Slot */
static int tx_i_index = 0; /* Transmit Interrupt Queue Index */
static int tx_u_index = 0; /* Transmit User Queue Index */
static int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */
#undef INFO_405_ENET
#ifdef INFO_405_ENET
static int packetSent = 0;
static int packetReceived = 0;
static int packetHandled = 0;
#endif
static char emac_hwd_addr[ENET_ADDR_LENGTH];
static bd_t *bis_save = NULL; /* for eth_init upon mal error */
static uint32_t mal_ier;
static int is_receiving = 0; /* sync with eth interrupt */
static int print_speed = 1; /* print speed message upon start */
#if !defined(CONFIG_NET_MULTI)
struct eth_device *emac0_dev;
#endif
/*-----------------------------------------------------------------------------+
* Prototypes and externals.
*-----------------------------------------------------------------------------*/
static void enet_rcv (unsigned long malisr);
static int enetInt(void);
static void mal_err (unsigned long isr, unsigned long uic, unsigned long mal_def,
unsigned long mal_errr);
static void emac_err (unsigned long isr);
static void enet_rcv (struct eth_device *dev, unsigned long malisr);
int enetInt (struct eth_device *dev);
static void mal_err (struct eth_device *dev, unsigned long isr,
unsigned long uic, unsigned long maldef,
unsigned long mal_errr);
static void emac_err (struct eth_device *dev, unsigned long isr);
/*-----------------------------------------------------------------------------+
| ppc_405x_eth_halt
| Disable MAL channel, and EMACn
|
|
+-----------------------------------------------------------------------------*/
static void ppc_4xx_eth_halt (struct eth_device *dev)
{
mtdcr (malier, 0x00000000); /* disable mal interrupts */
out32 (EMAC_IER, 0x00000000); /* disable emac interrupts */
EMAC_405_HW_PST hw_p = dev->priv;
uint32_t failsafe = 10000;
/* 1st reset MAL */
mtdcr (malmcr, MAL_CR_MMSR);
mtdcr (malier, 0x00000000); /* disable mal interrupts */
out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
/* 1st reset MAL channel */
/* Note: writing a 0 to a channel has no effect */
mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
/* wait for reset */
while (mfdcr (malmcr) & MAL_CR_MMSR) {
};
while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
udelay (1000); /* Delay 1 MS so as not to hammer the register */
failsafe--;
if (failsafe == 0)
break;
}
/* EMAC RESET */
out32 (EMAC_M0, EMAC_M0_SRST);
out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
print_speed = 1; /* print speed message again next time */
}
hw_p->print_speed = 1; /* print speed message again next time */
return;
}
static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
{
......@@ -212,63 +184,108 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
unsigned long msr;
unsigned long speed;
unsigned long duplex;
unsigned long failsafe;
unsigned mode_reg;
unsigned short devnum;
unsigned short reg_short;
EMAC_405_HW_PST hw_p = dev->priv;
/* before doing anything, figure out if we have a MAC address */
/* if not, bail */
if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0)
return -1;
msr = mfmsr ();
mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
devnum = hw_p->devnum;
#ifdef INFO_405_ENET
/* AS.HARNOIS
* We should have :
* packetHandled <= packetReceived <= packetHandled+PKTBUFSRX
* In the most cases packetHandled = packetReceived, but it
* hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
* In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
* is possible that new packets (without relationship with
* current transfer) have got the time to arrived before
* netloop calls eth_halt
*/
printf ("About preceeding transfer:\n"
printf ("About preceeding transfer (eth%d):\n"
"- Sent packet number %d\n"
"- Received packet number %d\n"
"- Handled packet number %d\n",
packetSent, packetReceived, packetHandled);
packetSent = 0;
packetReceived = 0;
packetHandled = 0;
hw_p->devnum,
hw_p->stats.pkts_tx,
hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
hw_p->stats.pkts_tx = 0;
hw_p->stats.pkts_rx = 0;
hw_p->stats.pkts_handled = 0;
#endif
/* MAL RESET */
mtdcr (malmcr, MAL_CR_MMSR);
mtdcr (malmcr, MAL_CR_MMSR);
/* wait for reset */
while (mfdcr (malmcr) & MAL_CR_MMSR) {
};
#if defined(CONFIG_440)
/* set RMII mode */
out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
#endif /* CONFIG_440 */
/* MAL Channel RESET */
/* 1st reset MAL channel */
/* Note: writing a 0 to a channel has no effect */
mtdcr (maltxcarr, (MAL_TXRX_CASR >> (hw_p->devnum * 2)));
mtdcr (malrxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
/* wait for reset */
/* TBS: should have udelay and failsafe here */
failsafe = 10000;
/* wait for reset */
while (mfdcr (malmcr) & MAL_CR_MMSR) {
};
while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
udelay (1000); /* Delay 1 MS so as not to hammer the register */
failsafe--;
if (failsafe == 0)
break;
tx_err_index = 0; /* Transmit Error Index for tx_err_log */
rx_err_index = 0; /* Receive Error Index for rx_err_log */
}
rx_slot = 0; /* MAL Receive Slot */
rx_i_index = 0; /* Receive Interrupt Queue Index */
rx_u_index = 0; /* Receive User Queue Index */
hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
tx_slot = 0; /* MAL Transmit Slot */
tx_i_index = 0; /* Transmit Interrupt Queue Index */
tx_u_index = 0; /* Transmit User Queue Index */
hw_p->rx_slot = 0; /* MAL Receive Slot */
hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
hw_p->rx_u_index = 0; /* Receive User Queue Index */
#if defined(CONFIG_440)
/* set RMII mode */
out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
#endif /* CONFIG_440 */
hw_p->tx_slot = 0; /* MAL Transmit Slot */
hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
hw_p->tx_u_index = 0; /* Transmit User Queue Index */
/* EMAC RESET */
out32 (EMAC_M0, EMAC_M0_SRST);
__asm__ volatile ("eieio");
/* reset emac so we have access to the phy */
out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
__asm__ volatile ("eieio");
failsafe = 1000;
while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
udelay (1000);
failsafe--;
}
#if defined(CONFIG_NET_MULTI)
reg = hw_p->devnum ? CONFIG_PHY1_ADDR : CONFIG_PHY_ADDR;
#else
reg = CONFIG_PHY_ADDR;
#endif
/* wait for PHY to complete auto negotiation */
reg_short = 0;
#ifndef CONFIG_CS8952_PHY
miiphy_read (CONFIG_PHY_ADDR, PHY_BMSR, &reg_short);
miiphy_read (reg, PHY_BMSR, &reg_short);
/*
* Wait if PHY is able of autonegotiation and autonegotiation is not complete
* Wait if PHY is capable of autonegotiation and autonegotiation is not complete
*/
if ((reg_short & PHY_BMSR_AUTN_ABLE)
&& !(reg_short & PHY_BMSR_AUTN_COMP)) {
......@@ -283,36 +300,39 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
break;
}
if ((i++ % 1000) == 0)
if ((i++ % 1000) == 0) {
putc ('.');
}
udelay (1000); /* 1 ms */
miiphy_read (CONFIG_PHY_ADDR, PHY_BMSR, &reg_short);
miiphy_read (reg, PHY_BMSR, &reg_short);
}
puts (" done\n");
udelay (500000); /* another 500 ms (results in faster booting) */
}
#endif
speed = miiphy_speed (CONFIG_PHY_ADDR);
duplex = miiphy_duplex (CONFIG_PHY_ADDR);
if (print_speed) {
print_speed = 0;
speed = miiphy_speed (reg);
duplex = miiphy_duplex (reg);
if (hw_p->print_speed) {
hw_p->print_speed = 0;
printf ("ENET Speed is %d Mbps - %s duplex connection\n",
(int) speed, (duplex == HALF) ? "HALF" : "FULL");
}
/* set the Mal configuration reg */
#if defined(CONFIG_440)
/* Errata 1.12: MAL_1 -- Disable MAL bursting */
if( get_pvr() == PVR_440GP_RB )
mtdcr (malmcr, MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
if( get_pvr() == PVR_440GP_RB)
mtdcr (malmcr, MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
else
#else
mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
#endif
/* Free "old" buffers */
if (alloc_tx_buf) free(alloc_tx_buf);
if (alloc_rx_buf) free(alloc_rx_buf);
if (hw_p->alloc_tx_buf)
free (hw_p->alloc_tx_buf);
if (hw_p->alloc_rx_buf)
free (hw_p->alloc_rx_buf);
/*
* Malloc MAL buffer desciptors, make sure they are
......@@ -320,93 +340,108 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
* (401/403/IOP480 = 16, 405 = 32)
* and doesn't cross cache block boundaries.
*/
alloc_tx_buf = (mal_desc_t *)malloc((sizeof(mal_desc_t) * NUM_TX_BUFF) +
((2 * CFG_CACHELINE_SIZE) - 2));
if (((int)alloc_tx_buf & CACHELINE_MASK) != 0) {
tx = (mal_desc_t *)((int)alloc_tx_buf + CFG_CACHELINE_SIZE -
((int)alloc_tx_buf & CACHELINE_MASK));
hw_p->alloc_tx_buf =
(mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
((2 * CFG_CACHELINE_SIZE) - 2));
if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
hw_p->tx =
(mal_desc_t *) ((int) hw_p->alloc_tx_buf +
CFG_CACHELINE_SIZE -
((int) hw_p->
alloc_tx_buf & CACHELINE_MASK));
} else {
tx = alloc_tx_buf;
hw_p->tx = hw_p->alloc_tx_buf;
}
alloc_rx_buf = (mal_desc_t *)malloc((sizeof(mal_desc_t) * NUM_RX_BUFF) +
((2 * CFG_CACHELINE_SIZE) - 2));
if (((int)alloc_rx_buf & CACHELINE_MASK) != 0) {
rx = (mal_desc_t *)((int)alloc_rx_buf + CFG_CACHELINE_SIZE -
((int)alloc_rx_buf & CACHELINE_MASK));
hw_p->alloc_rx_buf =
(mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
((2 * CFG_CACHELINE_SIZE) - 2));
if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
hw_p->rx =
(mal_desc_t *) ((int) hw_p->alloc_rx_buf +
CFG_CACHELINE_SIZE -
((int) hw_p->
alloc_rx_buf & CACHELINE_MASK));
} else {
rx = alloc_rx_buf;
hw_p->rx = hw_p->alloc_rx_buf;
}
for (i = 0; i < NUM_TX_BUFF; i++) {
tx[i].ctrl = 0;
tx[i].data_len = 0;
if (first_init == 0)
txbuf_ptr = (char *) malloc (ENET_MAX_MTU_ALIGNED);
tx[i].data_ptr = txbuf_ptr;
hw_p->tx[i].ctrl = 0;
hw_p->tx[i].data_len = 0;
if (hw_p->first_init == 0)
hw_p->txbuf_ptr =
(char *) malloc (ENET_MAX_MTU_ALIGNED);
hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
if ((NUM_TX_BUFF - 1) == i)
tx[i].ctrl |= MAL_TX_CTRL_WRAP;
tx_run[i] = -1;
hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
hw_p->tx_run[i] = -1;
#if 0
printf ("TX_BUFF %d @ 0x%08lx\n", i, (ulong) tx[i].data_ptr);
printf ("TX_BUFF %d @ 0x%08lx\n", i,
(ulong) hw_p->tx[i].data_ptr);
#endif
}
for (i = 0; i < NUM_RX_BUFF; i++) {
rx[i].ctrl = 0;
rx[i].data_len = 0;
hw_p->rx[i].ctrl = 0;
hw_p->rx[i].data_len = 0;
/* rx[i].data_ptr = (char *) &rx_buff[i]; */
rx[i].data_ptr = (char *) NetRxPackets[i];
hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
if ((NUM_RX_BUFF - 1) == i)
rx[i].ctrl |= MAL_RX_CTRL_WRAP;
rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
rx_ready[i] = -1;
hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
hw_p->rx_ready[i] = -1;
#if 0
printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
#endif
}
memcpy (emac_hwd_addr, bis->bi_enetaddr, ENET_ADDR_LENGTH);
reg = 0x00000000;
reg |= emac_hwd_addr[0]; /* set high address */
reg |= dev->enetaddr[0]; /* set high address */
reg = reg << 8;
reg |= emac_hwd_addr[1];
reg |= dev->enetaddr[1];
out32 (EMAC_IAH, reg);
out32 (EMAC_IAH + hw_p->hw_addr, reg);
reg = 0x00000000;
reg |= emac_hwd_addr[2]; /* set low address */
reg |= dev->enetaddr[2]; /* set low address */
reg = reg << 8;
reg |= emac_hwd_addr[3];
reg |= dev->enetaddr[3];
reg = reg << 8;
reg |= emac_hwd_addr[4];
reg |= dev->enetaddr[4];
reg = reg << 8;
reg |= emac_hwd_addr[5];
out32 (EMAC_IAL, reg);
/* setup MAL tx & rx channel pointers */
mtdcr (maltxctp0r, tx);
mtdcr (malrxctp0r, rx);
/* Reset transmit and receive channels */
mtdcr (malrxcarr, 0x80000000); /* 2 channels */
mtdcr (maltxcarr, 0x80000000); /* 2 channels */
reg |= dev->enetaddr[5];
out32 (EMAC_IAL + hw_p->hw_addr, reg);
switch (devnum) {
case 1:
/* setup MAL tx & rx channel pointers */
/* For 405EP, the EMAC1 tx channel 0 is MAL tx channel 2 */
mtdcr (maltxctp2r, hw_p->tx);
mtdcr (malrxctp1r, hw_p->rx);
/* set RX buffer size */
mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
break;
case 0:
default:
/* setup MAL tx & rx channel pointers */
mtdcr (maltxctp0r, hw_p->tx);
mtdcr (malrxctp0r, hw_p->rx);
/* set RX buffer size */
mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
break;
}
/* Enable MAL transmit and receive channels */
mtdcr (maltxcasr, 0x80000000); /* 1 channel */
mtdcr (malrxcasr, 0x80000000); /* 1 channel */
/* set RX buffer size */
mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum * 2)));
mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
/* set transmit enable & receive enable */
out32 (EMAC_M0, EMAC_M0_TXE | EMAC_M0_RXE);
out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
/* set receive fifo to 4k and tx fifo to 2k */
mode_reg = EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
mode_reg = in32 (EMAC_M1 + hw_p->hw_addr);
mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
/* set speed */
if (speed == _100BASET)
......@@ -416,7 +451,7 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
if (duplex == FULL)
mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
out32 (EMAC_M1, mode_reg);
out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
#if defined(CONFIG_440)
/* set speed in the ZMII bridge */
......@@ -427,67 +462,53 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
#endif
/* Enable broadcast and indvidual address */
out32 (EMAC_RXM, EMAC_RMR_BAE | EMAC_RMR_IAE
/*| EMAC_RMR_ARRP| EMAC_RMR_SFCS | EMAC_RMR_SP */ );
/* TBS: enabling runts as some misbehaved nics will send runts */
out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
/* we probably need to set the tx mode1 reg? maybe at tx time */
/* set transmit request threshold register */
out32 (EMAC_TRTR, 0x18000000); /* 256 byte threshold */
out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
/* set receive low/high water mark register */
#if defined(CONFIG_440)
/* 440GP has a 64 byte burst length */
out32 (EMAC_RX_HI_LO_WMARK, 0x80009000);
out32 (EMAC_TXM1, 0xf8640000);
#else /* CONFIG_440 */
out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
#else
/* 405s have a 16 byte burst length */
out32 (EMAC_RX_HI_LO_WMARK, 0x0f002000);
#endif /* CONFIG_440 */
out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
#endif
/* Frame gap set */
out32 (EMAC_I_FRAME_GAP_REG, 0x00000008);
out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
/* Set EMAC IER */
hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS |
EMAC_ISR_ORE | EMAC_ISR_IRE;
if (speed == _100BASET)
hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
if (first_init == 0) {
if (hw_p->first_init == 0) {
/*
* Connect interrupt service routines
*/
irq_install_handler (VECNUM_EWU0, (interrupt_handler_t *) enetInt, NULL);
irq_install_handler (VECNUM_MS, (interrupt_handler_t *) enetInt, NULL);
irq_install_handler (VECNUM_MTE, (interrupt_handler_t *) enetInt, NULL);
irq_install_handler (VECNUM_MRE, (interrupt_handler_t *) enetInt, NULL);
irq_install_handler (VECNUM_TXDE, (interrupt_handler_t *) enetInt, NULL);
irq_install_handler (VECNUM_RXDE, (interrupt_handler_t *) enetInt, NULL);
irq_install_handler (VECNUM_ETH0, (interrupt_handler_t *) enetInt, NULL);
#if !defined(CONFIG_405EP)
/* 405EP has one EWU interrupt */
irq_install_handler (VECNUM_EWU0 + (hw_p->devnum * 2),
(interrupt_handler_t *) enetInt, dev);
#endif
irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
(interrupt_handler_t *) enetInt, dev);
}
/* set up interrupt handler */
/* setup interrupt controler to take interrupts from the MAL &
EMAC */
mtdcr (uicsr, 0xffffffff); /* clear pending interrupts */
mtdcr (uicer, mfdcr (uicer) | MAL_UIC_DEF | EMAC_UIC_DEF);
/* set the MAL IER ??? names may change with new spec ??? */
mal_ier = MAL_IER_DE | MAL_IER_NE | MAL_IER_TE | MAL_IER_OPBE |
MAL_IER_PLBE;
mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
mtdcr (malier, mal_ier);
/* Set EMAC IER */
emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS |