Commit 476a3143 authored by Tom Rini's avatar Tom Rini
Browse files

Merge tag 'xilinx-for-v2019.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx/FPGA changes for v2019.10

fpga:
- Xilinx virtex2 cleanup
- Altera cyclon2 cleanup

zynq:
- Minor Kconfig cleanup
- Add psu_init configuration for Z-turn board

zynqmp:
- Add support for pmufw config passing to PMU
- script for psu_init conversion
- zcu1275 renaming

xilinx:
- Add support for UltraZed-EV SoM
parents dcf722ec cd228cc0
......@@ -240,6 +240,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zybo-z7.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
avnet-ultra96-rev1.dtb \
avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \
zynqmp-mini.dtb \
zynqmp-mini-emmc0.dtb \
zynqmp-mini-emmc1.dtb \
......@@ -253,10 +254,10 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-zcu104-revC.dtb \
zynqmp-zcu106-revA.dtb \
zynqmp-zcu111-revA.dtb \
zynqmp-zcu1275-revA.dtb \
zynqmp-zcu1275-revB.dtb \
zynqmp-zc1232-revA.dtb \
zynqmp-zc1254-revA.dtb \
zynqmp-zc1275-revA.dtb \
zynqmp-zc1275-revB.dtb \
zynqmp-zc1751-xm015-dc1.dtb \
zynqmp-zc1751-xm016-dc2.dtb \
zynqmp-zc1751-xm017-dc3.dtb \
......
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* UltraZed-EV Carrier Card v1 (based on the UltraZed-EV SoM)
* http://ultrazed.org/product/ultrazed-ev-carrier-card
*/
/dts-v1/;
#include "avnet-ultrazedev-som-v1.0.dtsi"
/ {
model = "Avnet UltraZed EV Carrier Card v1.0";
compatible = "avnet,ultrazedev-cc-v1.0-ultrazedev-som-v1.0",
"xlnx,zynqmp";
chosen {
stdout-path = "serial0:115200n8";
xlnx,eeprom = &eeprom;
};
aliases {
ethernet0 = &gem3;
serial0 = &uart0;
};
};
&uart0 {
device_type = "serial";
status = "okay";
};
&i2c_cc {
/* Microchip 24AA025E48T-I/OT: 2K I2C Serial EEPROM with EUI-48 */
eeprom: eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
};
/* IDT Versa Clock 5P49V5935B */
vc5: clock-generator@6a {
compatible = "idt,5p49v5935";
reg = <0x6a>;
#clock-cells = <1>;
};
};
/* Ethernet RJ-45 */
&gem3 {
status = "okay";
};
/* microSD card slot */
&sdhci1 {
status = "okay";
xlnx,mio_bank = <1>;
clock-frequency = <199998000>;
max-frequency = <50000000>;
no-1-8-v;
disable-wp;
};
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* UltraZed-EV SoM v1
* http://ultrazed.org/product/ultrazed-ev
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
/ {
model = "Avnet UltraZed EV SoM v1.0";
compatible = "avnet,ultrazedev-som-v1.0", "xlnx,zynqmp";
memory {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, /* 2 GB @ offset 0 */
<0x8 0x0 0x0 0x80000000>; /* 2 GB @ offset 32GB */
};
};
&i2c1 {
clock-frequency = <400000>;
status = "okay";
i2cswitch@70 {
compatible = "nxp,pca9543";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
/* I2C connected to Carrier Card via JX3A1/JX3C1 */
i2c_cc: i2c@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
/* Marvell 88E1512-A0-NNP2I000 Ethernet PHY */
&gem3 {
phy-mode = "rgmii-id";
phy-handle = <&gem3phy>;
gem3phy: ethernet-phy@0 {
reg = <0>;
};
};
/* Micron MTFC8GAKAJCN-4M 8 GB eMMC */
&sdhci0 {
status = "okay";
xlnx,mio_bank = <0>;
clock-frequency = <199998000>;
};
// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Xilinx ZynqMP ZC1275
* dts file for Xilinx ZynqMP ZCU1275
*
* (C) Copyright 2017 - 2018, Xilinx, Inc.
*
......@@ -14,8 +14,9 @@
#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP ZC1275 RevA";
compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
model = "ZynqMP ZCU1275 RevA";
compatible = "xlnx,zynqmp-zcu1275-revA", "xlnx,zynqmp-zcu1275",
"xlnx,zynqmp";
aliases {
serial0 = &uart0;
......
// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx ZynqMP ZC1275 RevB
* dts file for Xilinx ZynqMP ZCU1275 RevB
*
* (C) Copyright 2018, Xilinx, Inc.
*
......@@ -14,8 +14,9 @@
#include "zynqmp-clk-ccf.dtsi"
/ {
model = "ZynqMP ZC1275 RevB";
compatible = "xlnx,zynqmp-zc1275-revB", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
model = "ZynqMP ZCU1275 RevB";
compatible = "xlnx,zynqmp-zcu1275-revB", "xlnx,zynqmp-zcu1275",
"xlnx,zynqmp";
aliases {
serial0 = &uart0;
......
......@@ -65,6 +65,24 @@ config PMUFW_INIT_FILE
Include external PMUFW (Platform Management Unit FirmWare) to
a Xilinx bootable image (boot.bin).
config ZYNQMP_SPL_PM_CFG_OBJ_FILE
string "PMU firmware configuration object to load at runtime by SPL"
depends on SPL
help
Path to a binary PMU firmware configuration object to be linked
into U-Boot SPL and loaded at runtime into the PMU firmware.
The ZynqMP Power Management Unit (PMU) needs a configuration
object for most SoC peripherals to work. To have it loaded by
U-Boot SPL set here the file name (absolute path or relative to
the top source tree) of your configuration, which must be a
binary blob. It will be linked in the SPL binary and loaded
into the PMU firmware by U-Boot SPL during board
initialization.
Leave this option empty if your PMU firmware has a hard-coded
configuration object or you are loading it by any other means.
config ZYNQMP_USB
bool "Configure ZynqMP USB"
......
......@@ -8,3 +8,7 @@ obj-y += cpu.o
obj-$(CONFIG_MP) += mp.o
obj-$(CONFIG_SPL_BUILD) += spl.o handoff.o
obj-$(CONFIG_ZYNQMP_PSU_INIT_ENABLED) += psu_spl_init.o
ifneq ($(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE),"")
obj-$(CONFIG_SPL_BUILD) += pmu_ipc.o
endif
......@@ -72,4 +72,6 @@ int chip_id(unsigned char id);
void tcm_init(u8 mode);
#endif
void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size);
#endif /* _ASM_ARCH_SYS_PROTO_H */
// SPDX-License-Identifier: GPL-2.0+
/*
* Inter-Processor Communication with the Platform Management Unit (PMU)
* firmware.
*
* (C) Copyright 2019 Luca Ceresoli
* Luca Ceresoli <luca@lucaceresoli.net>
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
/* IPI bitmasks, register base and register offsets */
#define IPI_BIT_MASK_APU 0x00001
#define IPI_BIT_MASK_PMU0 0x10000
#define IPI_REG_BASE_APU 0xFF300000
#define IPI_REG_BASE_PMU0 0xFF330000
#define IPI_REG_OFFSET_TRIG 0x00
#define IPI_REG_OFFSET_OBR 0x04
/* IPI mailbox buffer offsets */
#define IPI_BUF_BASE_APU 0xFF990400
#define IPI_BUF_OFFSET_TARGET_PMU 0x1C0
#define IPI_BUF_OFFSET_REQ 0x00
#define IPI_BUF_OFFSET_RESP 0x20
#define PMUFW_PAYLOAD_ARG_CNT 8
/* PMUFW commands */
#define PMUFW_CMD_SET_CONFIGURATION 2
static void pmu_ipc_send_request(const u32 *req, size_t req_len)
{
u32 *mbx = (u32 *)(IPI_BUF_BASE_APU +
IPI_BUF_OFFSET_TARGET_PMU +
IPI_BUF_OFFSET_REQ);
size_t i;
for (i = 0; i < req_len; i++)
writel(req[i], &mbx[i]);
}
static void pmu_ipc_read_response(unsigned int *value, size_t count)
{
u32 *mbx = (u32 *)(IPI_BUF_BASE_APU +
IPI_BUF_OFFSET_TARGET_PMU +
IPI_BUF_OFFSET_RESP);
size_t i;
for (i = 0; i < count; i++)
value[i] = readl(&mbx[i]);
}
/**
* Send request to PMU and get the response.
*
* @req: Request buffer. Byte 0 is the API ID, other bytes are optional
* parameters.
* @req_len: Request length in number of 32-bit words.
* @res: Response buffer. Byte 0 is the error code, other bytes are
* optional parameters. Optional, if @res_maxlen==0 the parameters
* will not be read.
* @res_maxlen: Space allocated for the response in number of 32-bit words.
*
* @return Error code returned by the PMU (i.e. the first word of the response)
*/
static int pmu_ipc_request(const u32 *req, size_t req_len,
u32 *res, size_t res_maxlen)
{
u32 status;
if (req_len > PMUFW_PAYLOAD_ARG_CNT ||
res_maxlen > PMUFW_PAYLOAD_ARG_CNT)
return -EINVAL;
pmu_ipc_send_request(req, req_len);
/* Raise Inter-Processor Interrupt to PMU and wait for response */
writel(IPI_BIT_MASK_PMU0, IPI_REG_BASE_APU + IPI_REG_OFFSET_TRIG);
do {
status = readl(IPI_REG_BASE_APU + IPI_REG_OFFSET_OBR);
} while (status & IPI_BIT_MASK_PMU0);
pmu_ipc_read_response(res, res_maxlen);
return 0;
}
/**
* Send a configuration object to the PMU firmware.
*
* @cfg_obj: Pointer to the configuration object
* @size: Size of @cfg_obj in bytes
*/
void zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size)
{
const u32 request[] = {
PMUFW_CMD_SET_CONFIGURATION,
(u32)((u64)cfg_obj)
};
u32 response;
int err;
printf("Loading PMUFW cfg obj (%ld bytes)\n", size);
err = pmu_ipc_request(request, ARRAY_SIZE(request), &response, 1);
if (err)
panic("Cannot load PMUFW configuration object (%d)\n", err);
if (response != 0)
panic("PMUFW returned 0x%08x status!\n", response);
}
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) Xilinx, Inc.
*/
#include <asm/arch/ps7_init_gpl.h>
static unsigned long ps7_pll_init_data[] = {
EMIT_WRITE(0xF8000008, 0x0000DF0DU),
EMIT_MASKWRITE(0xF8000110, 0x003FFFF0U, 0x000FA220U),
EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000010U),
EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000001U),
EMIT_MASKWRITE(0xF8000100, 0x00000001U, 0x00000000U),
EMIT_MASKPOLL(0xF800010C, 0x00000001U),
EMIT_MASKWRITE(0xF8000100, 0x00000010U, 0x00000000U),
EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
EMIT_MASKWRITE(0xF8000114, 0x003FFFF0U, 0x0012C220U),
EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x00020000U),
EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000010U),
EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000001U),
EMIT_MASKWRITE(0xF8000104, 0x00000001U, 0x00000000U),
EMIT_MASKPOLL(0xF800010C, 0x00000002U),
EMIT_MASKWRITE(0xF8000104, 0x00000010U, 0x00000000U),
EMIT_MASKWRITE(0xF8000124, 0xFFF00003U, 0x0C200003U),
EMIT_MASKWRITE(0xF8000118, 0x003FFFF0U, 0x001452C0U),
EMIT_MASKWRITE(0xF8000108, 0x0007F000U, 0x0001E000U),
EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000010U),
EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000001U),
EMIT_MASKWRITE(0xF8000108, 0x00000001U, 0x00000000U),
EMIT_MASKPOLL(0xF800010C, 0x00000004U),
EMIT_MASKWRITE(0xF8000108, 0x00000010U, 0x00000000U),
EMIT_WRITE(0xF8000004, 0x0000767BU),
EMIT_EXIT(),
};
static unsigned long ps7_clock_init_data[] = {
EMIT_WRITE(0xF8000008, 0x0000DF0DU),
EMIT_MASKWRITE(0xF8000128, 0x03F03F01U, 0x00700F01U),
EMIT_MASKWRITE(0xF8000138, 0x00000011U, 0x00000001U),
EMIT_MASKWRITE(0xF8000140, 0x03F03F71U, 0x00100801U),
EMIT_MASKWRITE(0xF800014C, 0x00003F31U, 0x00000501U),
EMIT_MASKWRITE(0xF8000150, 0x00003F33U, 0x00001401U),
EMIT_MASKWRITE(0xF8000154, 0x00003F33U, 0x00000A03U),
EMIT_MASKWRITE(0xF800015C, 0x03F03F33U, 0x00200501U),
EMIT_MASKWRITE(0xF8000160, 0x007F007FU, 0x00000000U),
EMIT_MASKWRITE(0xF8000168, 0x00003F31U, 0x00000501U),
EMIT_MASKWRITE(0xF8000170, 0x03F03F30U, 0x00200500U),
EMIT_MASKWRITE(0xF8000180, 0x03F03F30U, 0x00400500U),
EMIT_MASKWRITE(0xF80001C4, 0x00000001U, 0x00000001U),
EMIT_MASKWRITE(0xF800012C, 0x01FFCCCDU, 0x01FD044DU),
EMIT_WRITE(0xF8000004, 0x0000767BU),
EMIT_EXIT(),
};
static unsigned long ps7_ddr_init_data[] = {
EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000080U),
EMIT_MASKWRITE(0xF8006004, 0x0007FFFFU, 0x00001082U),
EMIT_MASKWRITE(0xF8006008, 0x03FFFFFFU, 0x03C0780FU),
EMIT_MASKWRITE(0xF800600C, 0x03FFFFFFU, 0x02001001U),
EMIT_MASKWRITE(0xF8006010, 0x03FFFFFFU, 0x00014001U),
EMIT_MASKWRITE(0xF8006014, 0x001FFFFFU, 0x0004285BU),
EMIT_MASKWRITE(0xF8006018, 0xF7FFFFFFU, 0x44E458D3U),
EMIT_MASKWRITE(0xF800601C, 0xFFFFFFFFU, 0x7282BCE5U),
EMIT_MASKWRITE(0xF8006020, 0x7FDFFFFCU, 0x270872D0U),
EMIT_MASKWRITE(0xF8006024, 0x0FFFFFC3U, 0x00000000U),
EMIT_MASKWRITE(0xF8006028, 0x00003FFFU, 0x00002007U),
EMIT_MASKWRITE(0xF800602C, 0xFFFFFFFFU, 0x00000008U),
EMIT_MASKWRITE(0xF8006030, 0xFFFFFFFFU, 0x00040B30U),
EMIT_MASKWRITE(0xF8006034, 0x13FF3FFFU, 0x000116D4U),
EMIT_MASKWRITE(0xF8006038, 0x00000003U, 0x00000000U),
EMIT_MASKWRITE(0xF800603C, 0x000FFFFFU, 0x00000777U),
EMIT_MASKWRITE(0xF8006040, 0xFFFFFFFFU, 0xFFF00000U),
EMIT_MASKWRITE(0xF8006044, 0x0FFFFFFFU, 0x0F666666U),
EMIT_MASKWRITE(0xF8006048, 0x0003F03FU, 0x0003C008U),
EMIT_MASKWRITE(0xF8006050, 0xFF0F8FFFU, 0x77010800U),
EMIT_MASKWRITE(0xF8006058, 0x00010000U, 0x00000000U),
EMIT_MASKWRITE(0xF800605C, 0x0000FFFFU, 0x00005003U),
EMIT_MASKWRITE(0xF8006060, 0x000017FFU, 0x0000003EU),
EMIT_MASKWRITE(0xF8006064, 0x00021FE0U, 0x00020000U),
EMIT_MASKWRITE(0xF8006068, 0x03FFFFFFU, 0x00284141U),
EMIT_MASKWRITE(0xF800606C, 0x0000FFFFU, 0x00001610U),
EMIT_MASKWRITE(0xF8006078, 0x03FFFFFFU, 0x00466111U),
EMIT_MASKWRITE(0xF800607C, 0x000FFFFFU, 0x00032222U),
EMIT_MASKWRITE(0xF80060A4, 0xFFFFFFFFU, 0x10200802U),
EMIT_MASKWRITE(0xF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
EMIT_MASKWRITE(0xF80060AC, 0x000001FFU, 0x000001FEU),
EMIT_MASKWRITE(0xF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
EMIT_MASKWRITE(0xF80060B4, 0x00000200U, 0x00000200U),
EMIT_MASKWRITE(0xF80060B8, 0x01FFFFFFU, 0x00200066U),
EMIT_MASKWRITE(0xF80060C4, 0x00000003U, 0x00000000U),
EMIT_MASKWRITE(0xF80060C8, 0x000000FFU, 0x00000000U),
EMIT_MASKWRITE(0xF80060DC, 0x00000001U, 0x00000000U),
EMIT_MASKWRITE(0xF80060F0, 0x0000FFFFU, 0x00000000U),
EMIT_MASKWRITE(0xF80060F4, 0x0000000FU, 0x00000008U),
EMIT_MASKWRITE(0xF8006114, 0x000000FFU, 0x00000000U),
EMIT_MASKWRITE(0xF8006118, 0x7FFFFFCFU, 0x40000001U),
EMIT_MASKWRITE(0xF800611C, 0x7FFFFFCFU, 0x40000001U),
EMIT_MASKWRITE(0xF8006120, 0x7FFFFFCFU, 0x40000001U),
EMIT_MASKWRITE(0xF8006124, 0x7FFFFFCFU, 0x40000001U),
EMIT_MASKWRITE(0xF800612C, 0x000FFFFFU, 0x0002A81FU),
EMIT_MASKWRITE(0xF8006130, 0x000FFFFFU, 0x00029822U),
EMIT_MASKWRITE(0xF8006134, 0x000FFFFFU, 0x00026C10U),
EMIT_MASKWRITE(0xF8006138, 0x000FFFFFU, 0x00026013U),
EMIT_MASKWRITE(0xF8006140, 0x000FFFFFU, 0x00000035U),
EMIT_MASKWRITE(0xF8006144, 0x000FFFFFU, 0x00000035U),
EMIT_MASKWRITE(0xF8006148, 0x000FFFFFU, 0x00000035U),
EMIT_MASKWRITE(0xF800614C, 0x000FFFFFU, 0x00000035U),
EMIT_MASKWRITE(0xF8006154, 0x000FFFFFU, 0x0000009FU),
EMIT_MASKWRITE(0xF8006158, 0x000FFFFFU, 0x000000A2U),
EMIT_MASKWRITE(0xF800615C, 0x000FFFFFU, 0x00000090U),
EMIT_MASKWRITE(0xF8006160, 0x000FFFFFU, 0x00000093U),
EMIT_MASKWRITE(0xF8006168, 0x001FFFFFU, 0x000000FFU),
EMIT_MASKWRITE(0xF800616C, 0x001FFFFFU, 0x000000FBU),
EMIT_MASKWRITE(0xF8006170, 0x001FFFFFU, 0x000000F0U),
EMIT_MASKWRITE(0xF8006174, 0x001FFFFFU, 0x000000EDU),
EMIT_MASKWRITE(0xF800617C, 0x000FFFFFU, 0x000000DFU),
EMIT_MASKWRITE(0xF8006180, 0x000FFFFFU, 0x000000E2U),
EMIT_MASKWRITE(0xF8006184, 0x000FFFFFU, 0x000000D0U),
EMIT_MASKWRITE(0xF8006188, 0x000FFFFFU, 0x000000D3U),
EMIT_MASKWRITE(0xF8006190, 0x6FFFFEFEU, 0x00040080U),
EMIT_MASKWRITE(0xF8006194, 0x000FFFFFU, 0x0001FC82U),
EMIT_MASKWRITE(0xF8006204, 0xFFFFFFFFU, 0x00000000U),
EMIT_MASKWRITE(0xF8006208, 0x000703FFU, 0x000003FFU),
EMIT_MASKWRITE(0xF800620C, 0x000703FFU, 0x000003FFU),
EMIT_MASKWRITE(0xF8006210, 0x000703FFU, 0x000003FFU),
EMIT_MASKWRITE(0xF8006214, 0x000703FFU, 0x000003FFU),
EMIT_MASKWRITE(0xF8006218, 0x000F03FFU, 0x000003FFU),
EMIT_MASKWRITE(0xF800621C, 0x000F03FFU, 0x000003FFU),
EMIT_MASKWRITE(0xF8006220, 0x000F03FFU, 0x000003FFU),
EMIT_MASKWRITE(0xF8006224, 0x000F03FFU, 0x000003FFU),
EMIT_MASKWRITE(0xF80062A8, 0x00000FF5U, 0x00000000U),
EMIT_MASKWRITE(0xF80062AC, 0xFFFFFFFFU, 0x00000000U),
EMIT_MASKWRITE(0xF80062B0, 0x003FFFFFU, 0x00005125U),
EMIT_MASKWRITE(0xF80062B4, 0x0003FFFFU, 0x000012A8U),
EMIT_MASKPOLL(0xF8000B74, 0x00002000U),
EMIT_MASKWRITE(0xF8006000, 0x0001FFFFU, 0x00000081U),
EMIT_MASKPOLL(0xF8006054, 0x00000007U),
EMIT_EXIT(),
};
static unsigned long ps7_mio_init_data[] = {
EMIT_WRITE(0xF8000008, 0x0000DF0DU),
EMIT_MASKWRITE(0xF8000B40, 0x00000FFFU, 0x00000600U),
EMIT_MASKWRITE(0xF8000B44, 0x00000FFFU, 0x00000600U),
EMIT_MASKWRITE(0xF8000B48, 0x00000FFFU, 0x00000672U),
EMIT_MASKWRITE(0xF8000B4C, 0x00000FFFU, 0x00000672U),
EMIT_MASKWRITE(0xF8000B50, 0x00000FFFU, 0x00000674U),
EMIT_MASKWRITE(0xF8000B54, 0x00000FFFU, 0x00000674U),
EMIT_MASKWRITE(0xF8000B58, 0x00000FFFU, 0x00000600U),
EMIT_MASKWRITE(0xF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
EMIT_MASKWRITE(0xF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
EMIT_MASKWRITE(0xF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
EMIT_MASKWRITE(0xF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
EMIT_MASKWRITE(0xF8000B6C, 0x00007FFFU, 0x00000260U),
EMIT_MASKWRITE(0xF8000B70, 0x00000001U, 0x00000001U),
EMIT_MASKWRITE(0xF8000B70, 0x00000021U, 0x00000020U),
EMIT_MASKWRITE(0xF8000B70, 0x07FEFFFFU, 0x00000823U),
EMIT_MASKWRITE(0xF8000700, 0x00003FFFU, 0x00001600U),
EMIT_MASKWRITE(0xF8000704, 0x00003FFFU, 0x00000602U),
EMIT_MASKWRITE(0xF8000708, 0x00003FFFU, 0x00000602U),
EMIT_MASKWRITE(0xF800070C, 0x00003FFFU, 0x00000602U),
EMIT_MASKWRITE(0xF8000710, 0x00003FFFU, 0x00000602U),
EMIT_MASKWRITE(0xF8000714, 0x00003FFFU, 0x00000602U),
EMIT_MASKWRITE(0xF8000718, 0x00003FFFU, 0x00000602U),
EMIT_MASKWRITE(0xF800071C, 0x00003FFFU, 0x00000600U),
EMIT_MASKWRITE(0xF8000720, 0x00003FFFU, 0x00000602U),
EMIT_MASKWRITE(0xF8000724, 0x00003FFFU, 0x00000600U),
EMIT_MASKWRITE(0xF8000728, 0x00003FFFU, 0x000016E1U),
EMIT_MASKWRITE(0xF800072C, 0x00003FFFU, 0x000016E0U),
EMIT_MASKWRITE(0xF8000730, 0x00003FFFU, 0x00001640U),
EMIT_MASKWRITE(0xF8000734, 0x00003FFFU, 0x00001640U),
EMIT_MASKWRITE(0xF8000738, 0x00003FFFU, 0x00001621U),
EMIT_MASKWRITE(0xF800073C, 0x00003FFFU, 0x00001620U),
EMIT_MASKWRITE(0xF8000740, 0x00003FFFU, 0x00001202U),
EMIT_MASKWRITE(0xF8000744, 0x00003FFFU, 0x00001202U),
EMIT_MASKWRITE(0xF8000748, 0x00003FFFU, 0x00001202U),
EMIT_MASKWRITE(0xF800074C, 0x00003FFFU, 0x00001202U),
EMIT_MASKWRITE(0xF8000750, 0x00003FFFU, 0x00001202U),
EMIT_MASKWRITE(0xF8000754, 0x00003FFFU, 0x00001202U),
EMIT_MASKWRITE(0xF8000758, 0x00003FFFU, 0x00001203U),
EMIT_MASKWRITE(0xF800075C, 0x00003FFFU, 0x00001203U),
EMIT_MASKWRITE(0xF8000760, 0x00003FFFU, 0x00001203U),
EMIT_MASKWRITE(0xF8000764, 0x00003FFFU, 0x00001203U),
EMIT_MASKWRITE(0xF8000768, 0x00003FFFU, 0x00001203U),
EMIT_MASKWRITE(0xF800076C, 0x00003FFFU, 0x00001203U),
EMIT_MASKWRITE(0xF8000770, 0x00003FFFU, 0x00001204U),
EMIT_MASKWRITE(0xF8000774, 0x00003FFFU, 0x00001205U),
EMIT_MASKWRITE(0xF8000778, 0x00003FFFU, 0x00001204U),
EMIT_MASKWRITE(0xF800077C, 0x00003FFFU, 0x00001205U),
EMIT_MASKWRITE(0xF8000780, 0x00003FFFU, 0x00001204U),
EMIT_MASKWRITE(0xF8000784, 0x00003FFFU, 0x00001204U),
EMIT_MASKWRITE(0xF8000788, 0x00003FFFU, 0x00001204U),
EMIT_MASKWRITE(0xF800078C, 0x00003FFFU, 0x00001204U),
EMIT_MASKWRITE(0xF8000790, 0x00003FFFU, 0x00001205U),
EMIT_MASKWRITE(0xF8000794, 0x00003FFFU, 0x00001204U),
EMIT_MASKWRITE(0xF8000798, 0x00003FFFU, 0x00001204U),
EMIT_MASKWRITE(0xF800079C, 0x00003FFFU, 0x00001204U),
EMIT_MASKWRITE(0xF80007A0, 0x00003FFFU, 0x00001280U),
EMIT_MASKWRITE(0xF80007A4, 0x00003FFFU, 0x00001280U),
EMIT_MASKWRITE(0xF80007A8, 0x00003FFFU, 0x00001280U),
EMIT_MASKWRITE(0xF80007AC, 0x00003FFFU, 0x00001280U),
EMIT_MASKWRITE(0xF80007B0, 0x00003FFFU, 0x00001280U),
EMIT_MASKWRITE(0xF80007B4, 0x00003FFFU, 0x00001280U),
EMIT_MASKWRITE(0xF80007B8, 0x00003F01U, 0x00000201U),
EMIT_MASKWRITE(0xF80007BC, 0x00003F01U, 0x00000201U),
EMIT_MASKWRITE(0xF80007C0, 0x00003FFFU, 0x000012E0U),
EMIT_MASKWRITE(0xF80007C4, 0x00003FFFU, 0x000012E1U),
EMIT_MASKWRITE(0xF80007C8, 0x00003FFFU, 0x00000200U),
EMIT_MASKWRITE(0xF80007CC, 0x00003FFFU, 0x00000200U),
EMIT_MASKWRITE(0xF80007D0, 0x00003FFFU, 0x00001280U),
EMIT_MASKWRITE(0xF80007D4, 0x00003FFFU, 0x00001280U),
EMIT_MASKWRITE(0xF8000830, 0x003F003FU, 0x002E002FU),
EMIT_WRITE(0xF8000004, 0x0000767BU),
EMIT_EXIT(),
};
static unsigned long ps7_peripherals_init_data[] = {
EMIT_WRITE(0xF8000008, 0x0000DF0DU),
EMIT_MASKWRITE(0xF8000B48, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000B4C, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000B50, 0x00000180U, 0x00000180U),
EMIT_MASKWRITE(0xF8000B54, 0x00000180U, 0x00000180U),
EMIT_WRITE(0xF8000004, 0x0000767BU),
EMIT_MASKWRITE(0xE0001034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0xE0001018, 0x0000FFFFU, 0x0000007CU),
EMIT_MASKWRITE(0xE0001000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0xE0001004, 0x000003FFU, 0x00000020U),
EMIT_MASKWRITE(0xE0000034, 0x000000FFU, 0x00000006U),
EMIT_MASKWRITE(0xE0000018, 0x0000FFFFU, 0x0000007CU),
EMIT_MASKWRITE(0xE0000000, 0x000001FFU, 0x00000017U),
EMIT_MASKWRITE(0xE0000004, 0x000003FFU, 0x00000020U),
EMIT_MASKWRITE(0xE000D000, 0x00080000U, 0x00080000U),
EMIT_MASKWRITE(0xF8007000, 0x20000000U, 0x00000000U),
EMIT_MASKWRITE(0xE000A244, 0x003FFFFFU, 0x00080000U),
EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370008U),
EMIT_MASKWRITE(0xE000A248, 0x003FFFFFU, 0x00080000U),
EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370000U),
EMIT_MASKDELAY(0xF8F00200, 1),
EMIT_MASKWRITE(0xE000A00C, 0x003F003FU, 0x00370008U),
EMIT_EXIT(),
};
static unsigned long ps7_post_config_0[] = {
EMIT_WRITE(0xF8000008, 0x0000DF0DU),
EMIT_MASKWRITE(0xF8000900, 0x0000000FU, 0x0000000FU),
EMIT_MASKWRITE(0xF8000240, 0xFFFFFFFFU, 0x00000000U),
EMIT_WRITE(0xF8000004, 0x0000767BU),
EMIT_EXIT(),
};
int ps7_post_config(void)
{
return ps7_config(ps7_post_config_0);
}
int ps7_init(void)
{