Commit 7e090b46 authored by Tom Rini's avatar Tom Rini
Browse files

Merge git://git.denx.de/u-boot-fsl-qoriq

Changes from rc2 tag
  - Support PCIe Gen4 driver of the Mobiveil IP
  - NXP LS1028A SoC and platform support
  - Few SPI related config updates
  - Distinguish the ecc val by chassis version and move the ecc addr to dts
  - sp805 watchdog support
parents e1a2ed71 e50663e8
......@@ -519,6 +519,7 @@ FREESCALE QORIQ
M: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
S: Maintained
T: git git://git.denx.de/u-boot-fsl-qoriq.git
F: drivers/watchdog/sp805_wdt.c
I2C
M: Heiko Schocher <hs@denx.de>
......
......@@ -1262,6 +1262,28 @@ config TARGET_LS1012AFRDM
development platform that supports the QorIQ LS1012A
Layerscape Architecture processor.
config TARGET_LS1028AQDS
bool "Support ls1028aqds"
select ARCH_LS1028A
select ARM64
select ARMV8_MULTIENTRY
help
Support for Freescale LS1028AQDS platform
The LS1028A Development System (QDS) is a high-performance
development platform that supports the QorIQ LS1028A
Layerscape Architecture processor.
config TARGET_LS1028ARDB
bool "Support ls1028ardb"
select ARCH_LS1028A
select ARM64
select ARMV8_MULTIENTRY
help
Support for Freescale LS1028ARDB platform
The LS1028A Development System (RDB) is a high-performance
development platform that supports the QorIQ LS1028A
Layerscape Architecture processor.
config TARGET_LS1088ARDB
bool "Support ls1088ardb"
select ARCH_LS1088A
......@@ -1666,6 +1688,7 @@ source "board/freescale/ls2080a/Kconfig"
source "board/freescale/ls2080aqds/Kconfig"
source "board/freescale/ls2080ardb/Kconfig"
source "board/freescale/ls1088a/Kconfig"
source "board/freescale/ls1028a/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1043aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
......
......@@ -104,6 +104,7 @@ config PSCI_RESET
!TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
!TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
!TARGET_LS1012AFRWY && \
!TARGET_LS1028ARDB && !TARGET_LS1028AQDS && \
!TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
!TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
!TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
......
......@@ -20,6 +20,40 @@ config ARCH_LS1012A
select SYS_I2C_MXC_I2C2
imply PANIC_HANG
config ARCH_LS1028A
bool
select ARMV8_SET_SMPEN
select FSL_LSCH3
select NXP_LSCH3_2
select SYS_FSL_HAS_CCI400
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
select SYS_FSL_DDR_LE
select SYS_FSL_DDR_VER_50
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
select FSL_TZASC_1
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
select SYS_I2C_MXC_I2C1
select SYS_I2C_MXC_I2C2
select SYS_I2C_MXC_I2C3
select SYS_I2C_MXC_I2C4
select SYS_I2C_MXC_I2C5
select SYS_I2C_MXC_I2C6
select SYS_I2C_MXC_I2C7
select SYS_I2C_MXC_I2C8
select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A008514 if !TFABOOT
select SYS_FSL_ERRATUM_A009663 if !TFABOOT
select SYS_FSL_ERRATUM_A009942 if !TFABOOT
imply PANIC_HANG
config ARCH_LS1043A
bool
select ARMV8_SET_SMPEN
......@@ -242,8 +276,9 @@ config FSL_LAYERSCAPE
config FSL_PCIE_COMPAT
string "PCIe compatible of Kernel DT"
depends on PCIE_LAYERSCAPE
depends on PCIE_LAYERSCAPE || PCIE_LAYERSCAPE_GEN4
default "fsl,ls1012a-pcie" if ARCH_LS1012A
default "fsl,ls1028a-pcie" if ARCH_LS1028A
default "fsl,ls1043a-pcie" if ARCH_LS1043A
default "fsl,ls1046a-pcie" if ARCH_LS1046A
default "fsl,ls2080a-pcie" if ARCH_LS2080A
......@@ -343,6 +378,7 @@ config SYS_FSL_ERRATUM_A010539
config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 2 if ARCH_LS1028A
default 4 if ARCH_LS1043A
default 4 if ARCH_LS1046A
default 16 if ARCH_LS2080A
......@@ -377,7 +413,7 @@ config QSPI_AHB_INIT
config SYS_CCI400_OFFSET
hex "Offset for CCI400 base"
depends on SYS_FSL_HAS_CCI400
default 0x3090000 if ARCH_LS1088A
default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
default 0x180000 if FSL_LSCH2
help
Offset for CCI400 base
......@@ -446,6 +482,7 @@ config CLUSTER_CLK_FREQ
config SYS_FSL_PCLK_DIV
int "Platform clock divider"
default 1 if ARCH_LS1028A
default 1 if ARCH_LS1043A
default 1 if ARCH_LS1046A
default 1 if ARCH_LS1088A
......
......@@ -48,3 +48,7 @@ endif
ifneq ($(CONFIG_ARCH_LS1088A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o
endif
ifneq ($(CONFIG_ARCH_LS1028A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1028a_serdes.o
endif
......@@ -58,6 +58,7 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
CPU_TYPE_ENTRY(LS1028A, LS1028A, 2),
CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
......@@ -246,17 +247,33 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
CONFIG_SYS_PCIE3_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
#endif
#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
CONFIG_SYS_PCIE4_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#endif
#ifdef SYS_PCIE5_PHYS_ADDR
{ SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
SYS_PCIE5_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#endif
#ifdef SYS_PCIE6_PHYS_ADDR
{ SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
SYS_PCIE6_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#endif
{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
CONFIG_SYS_FSL_WRIOP1_SIZE,
......@@ -341,11 +358,13 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
CONFIG_SYS_PCIE3_PHYS_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
#endif
{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
CONFIG_SYS_FSL_DRAM_SIZE3,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
......@@ -448,16 +467,20 @@ static void fix_pcie_mmu_map(void)
final_map[i].virt = 0x2800000000ULL;
final_map[i].size = 0x800000000ULL;
break;
#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR
case CONFIG_SYS_PCIE3_PHYS_ADDR:
final_map[i].phys = 0x3000000000ULL;
final_map[i].virt = 0x3000000000ULL;
final_map[i].size = 0x800000000ULL;
break;
#endif
#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
case CONFIG_SYS_PCIE4_PHYS_ADDR:
final_map[i].phys = 0x3800000000ULL;
final_map[i].virt = 0x3800000000ULL;
final_map[i].size = 0x800000000ULL;
break;
#endif
default:
break;
}
......@@ -785,12 +808,8 @@ enum env_location env_get_location(enum env_operation op, int prio)
if (prio)
return ENVL_UNKNOWN;
#ifdef CONFIG_CHAIN_OF_TRUST
/* Check Boot Mode
* If Boot Mode is Secure, return ENVL_NOWHERE
*/
if (fsl_check_boot_mode_secure() == 1)
goto done;
#ifdef CONFIG_ENV_IS_NOWHERE
return env_loc;
#endif
switch (src) {
......@@ -820,9 +839,6 @@ enum env_location env_get_location(enum env_operation op, int prio)
break;
}
#ifdef CONFIG_CHAIN_OF_TRUST
done:
#endif
return env_loc;
}
#endif /* CONFIG_TFABOOT */
......
......@@ -8,6 +8,7 @@ SoC overview
6. LS2088A
7. LS2081A
8. LX2160A
9. LS1028A
LS1043A
---------
......@@ -328,3 +329,53 @@ LX2160A SoC has 2 more similar SoC personalities
2)LX2080A, few difference w.r.t. LX2160A:
a) Eight 64-bit ARM v8 Cortex-A72 CPUs
LS1028A
--------
The QorIQ LS1028A processor integrates two 64-bit Arm Cortex-A72 cores with
a GPU and LCD controller, as well as two TSN-enabled Ethernet controllers and
a TSNenabled 4-port switch.
The high performance Cortex-A72 cores, performing above 16,000 CoreMarks,
combined with 2.5 Gbit Ethernet, PCI express Gen 3.0, SATA 3.0, USB 3.0 and
Octal/Quad SPI interfaces provide capabilities for a number of industrial and
embedded applications. The device provides excellent integration with the
new Time-Sensitive Networking standard, and enables a number of
TSN applications.
The LS1028A SoC includes the following function and features:
- Two 64-bit ARM v8 A72 CPUs
- Cache Coherent interconnect (CCI-400)
- One 32-bit DDR3L/DDR4 SDRAM memory controller with ECC
- eDP/Displayport interface
- Graphics processing unit
- One Configurable x4 SerDes
- Ethernet interfaces
- Non-switched: One Ethernet MAC supporting 2.5G, 1G, 100M, 10M, one
ethernet MAC supporting 1G, 100M, 10M.
- Switched: TSN IP to support four 2.5/1G interfaces.
- None of the MACs support MACSEC
- Support for RGMII, SGMII (and 1000Base-KX), SGMII 2.5x, QSGMII
- Support for 10G-SXGMII and 10G-QXGMII.
- Energy efficient Ethernet support (802.3az)
- IEEE 1588 support
- High-speed peripheral interfaces
- Two PCIe 3.0 controllers, one supporting x4 operation
- One serial ATA (SATA 3.0) controller
- Additional peripheral interfaces
- Two high-speed USB 2.0/3.0 controllers with integrated PHY each
supporting host or device modes
- Two Enhanced secure digital host controllers (SD/SDIO/eMMC)
- Two Serial peripheral interface (SPI) controllers
- Eight I2C controllers
- Two UART controllers
- Additional six Industrual UARTs (LPUART).
- One FlexSPI controller
- General Purpose IO (GPIO)
- Two CAN-FD interfaces
- Eight Flextimers with PWM I/O
- Support for hardware virtualization and partitioning enforcement
- Layerscape Trust Architecture
- Service Processor (SP) provides pre-boot initialization and secure-boot
capabilities
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
*/
#include <common.h>
#include <asm/arch/fsl_serdes.h>
struct serdes_config {
u32 protocol;
u8 lanes[SRDS_MAX_LANES];
u8 rcw_lanes[SRDS_MAX_LANES];
};
static struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{0xCC5B, {PCIE1, QSGMII_B, PCIE2, PCIE2} },
{0xEB99, {SGMII1, SGMII1, PCIE2, SATA1} },
{0xCC99, {SGMII1, SGMII1, PCIE2, PCIE2} },
{0xBB99, {SGMII1, SGMII1, PCIE2, PCIE1} },
{0x9999, {SGMII1, SGMII2, SGMII3, SGMII4} },
{0xEBCC, {PCIE1, PCIE1, PCIE2, SATA1} },
{0xCCCC, {PCIE1, PCIE1, PCIE2, PCIE2} },
{0xDDDD, {PCIE1, PCIE1, PCIE1, PCIE1} },
{}
};
static struct serdes_config *serdes_cfg_tbl[] = {
serdes1_cfg_tbl,
};
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
{
struct serdes_config *ptr;
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
ptr = serdes_cfg_tbl[serdes];
while (ptr->protocol) {
if (ptr->protocol == cfg)
return ptr->lanes[lane];
ptr++;
}
return 0;
}
int is_serdes_prtcl_valid(int serdes, u32 prtcl)
{
int i;
struct serdes_config *ptr;
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
ptr = serdes_cfg_tbl[serdes];
while (ptr->protocol) {
if (ptr->protocol == prtcl)
break;
ptr++;
}
if (!ptr->protocol)
return 0;
for (i = 0; i < SRDS_MAX_LANES; i++) {
if (ptr->lanes[i] != NONE)
return 1;
}
return 0;
}
......@@ -329,6 +329,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2088a-rdb-qspi.dtb \
fsl-ls1088a-rdb.dtb \
fsl-ls1088a-qds.dtb \
fsl-ls1028a-rdb.dtb \
fsl-ls1028a-qds.dtb \
fsl-lx2160a-rdb.dtb \
fsl-lx2160a-qds.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
......
......@@ -136,7 +136,9 @@
sata: sata@3200000 {
compatible = "fsl,ls1012a-ahci";
reg = <0x0 0x3200000 0x0 0x10000>;
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
0x0 0x20140520 0x0 0x4>; /* ecc sata addr */
reg-names = "sata-base", "ecc-addr";
interrupts = <0 69 4>;
clocks = <&clockgen 4 0>;
status = "disabled";
......
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP ls1028AQDS device tree source
*
* Copyright 2019 NXP
*
*/
/dts-v1/;
#include "fsl-ls1028a.dtsi"
/ {
model = "NXP Layerscape 1028a QDS Board";
compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
};
&dspi0 {
status = "okay";
};
&dspi1 {
status = "okay";
};
&dspi2 {
status = "okay";
};
&esdhc0 {
status = "okay";
};
&esdhc1 {
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
};
&i2c5 {
status = "okay";
};
&i2c6 {
status = "okay";
};
&i2c7 {
status = "okay";
};
&sata {
status = "okay";
};
&serial0 {
status = "okay";
};
&serial1 {
status = "okay";
};
&usb1 {
status = "okay";
};
&usb2 {
status = "okay";
};
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP ls1028ARDB device tree source
*
* Copyright 2019 NXP
*
*/
/dts-v1/;
#include "fsl-ls1028a.dtsi"
/ {
model = "NXP Layerscape 1028a RDB Board";
compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
};
&dspi0 {
status = "okay";
};
&dspi1 {
status = "okay";
};
&dspi2 {
status = "okay";
};
&esdhc0 {
status = "okay";
};
&esdhc1 {
status = "okay";
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
};
&i2c5 {
status = "okay";
};
&i2c6 {
status = "okay";
};
&i2c7 {
status = "okay";
};
&sata {
status = "okay";
};
&serial0 {
status = "okay";
};
&serial1 {
status = "okay";
};
&usb1 {
status = "okay";
};
&usb2 {
status = "okay";
};
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP ls1028a SOC common device tree source
*
* Copyright 2019 NXP
*
*/
/ {
compatible = "fsl,ls1028a";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "sysclk";
};
clockgen: clocking@1300000 {
compatible = "fsl,ls1028a-clockgen";
reg = <0x0 0x1300000 0x0 0xa0000>;
#clock-cells = <2>;
clocks = <&sysclk>;
};
memory@01080000 {
device_type = "memory";
reg = <0x00000000 0x01080000 0 0x80000000>;
/* DRAM space - 1, size : 2 GB DRAM */
};
gic: interrupt-controller@6000000 {
compatible = "arm,gic-v3";
reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
<0x0 0x06040000 0 0x40000>;
#interrupt-cells = <3>;
interrupt-controller;
interrupts = <1 9 0x4>;
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
<1 14 0x8>, /* Physical Non-Secure PPI, active-low */
<1 11 0x8>, /* Virtual PPI, active-low */
<1 10 0x8>; /* Hypervisor PPI, active-low */
};
fspi: flexspi@20C0000 {
compatible = "nxp,dn-fspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x20C0000 0x0 0x10000>,