Commit a8d60505 authored by Hou Zhiqiang's avatar Hou Zhiqiang Committed by Prabhakar Kushwaha
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armv8: lx2160a: add PCIe controller DT nodes



The LX2160A integrated 6 PCIe Gen4 controllers.
Signed-off-by: default avatarHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Bin Meng's avatarBin Meng <bmeng.cn@gmail.com>
Reviewed-by: default avatarPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
parent 1d341bc4
......@@ -176,4 +176,89 @@
status = "disabled";
};
pcie@3400000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03400000 0x0 0x80000 /* PAB registers */
0x00 0x03480000 0x0 0x40000 /* LUT registers */
0x00 0x034c0000 0x0 0x40000 /* PF control registers */
0x80 0x00000000 0x0 0x1000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
};
pcie@3500000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03500000 0x0 0x80000 /* PAB registers */
0x00 0x03580000 0x0 0x40000 /* LUT registers */
0x00 0x035c0000 0x0 0x40000 /* PF control registers */
0x88 0x00000000 0x0 0x1000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
num-lanes = <2>;
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>;
};
pcie@3600000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03600000 0x0 0x80000 /* PAB registers */
0x00 0x03680000 0x0 0x40000 /* LUT registers */
0x00 0x036c0000 0x0 0x40000 /* PF control registers */
0x90 0x00000000 0x0 0x1000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>;
};
pcie@3700000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03700000 0x0 0x80000 /* PAB registers */
0x00 0x03780000 0x0 0x40000 /* LUT registers */
0x00 0x037c0000 0x0 0x40000 /* PF control registers */
0x98 0x00000000 0x0 0x1000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>;
};
pcie@3800000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03800000 0x0 0x80000 /* PAB registers */
0x00 0x03880000 0x0 0x40000 /* LUT registers */
0x00 0x038c0000 0x0 0x40000 /* PF control registers */
0xa0 0x00000000 0x0 0x1000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>;
};
pcie@3900000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03900000 0x0 0x80000 /* PAB registers */
0x00 0x03980000 0x0 0x40000 /* LUT registers */
0x00 0x039c0000 0x0 0x40000 /* PF control registers */
0xa8 0x00000000 0x0 0x1000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>;
};
};
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