Commit ab2a98b1 authored by Daniel Schwierzeck's avatar Daniel Schwierzeck Committed by Shinya Kuribayashi
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MIPS: make cache operation mode configurable



Currently the cache operation mode is hard-coded to
CONF_CM_CACHABLE_NONCOHERENT. This is not appropiate for CPUs or SOCs
which operate at a different mode.

This patch makes the cache operation mode configurable via board config.
Signed-off-by: Daniel Schwierzeck's avatarDaniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Acked-by: default avatarThomas Langer <thomas.langer@lantiq.com>
Signed-off-by: default avatarShinya Kuribayashi <skuribay@pobox.com>
parent 7185adb4
......@@ -27,6 +27,10 @@
#include <asm/regdef.h>
#include <asm/mipsregs.h>
#ifndef CONFIG_SYS_MIPS_CACHE_MODE
#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
#endif
/*
* For the moment disable interrupts, mark the kernel mode and
* set ST0_KX so that the CPU does not spit fire when using
......@@ -249,7 +253,7 @@ reset:
nop
/* ... and enable them */
li t0, CONF_CM_CACHABLE_NONCOHERENT
li t0, CONFIG_SYS_MIPS_CACHE_MODE
mtc0 t0, CP0_CONFIG
#endif
......
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