Commit dcf722ec authored by Tom Rini's avatar Tom Rini
Browse files

Merge branch 'master' of git://git.denx.de/u-boot-sh

parents d0d07ba8 b5f563e5
......@@ -462,6 +462,76 @@
reg = <0 0xe6060000 0 0x50c>;
};
cmt0: timer@e60f0000 {
compatible = "renesas,r8a7795-cmt0",
"renesas,rcar-gen3-cmt0";
reg = <0 0xe60f0000 0 0x1004>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 303>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 303>;
status = "disabled";
};
cmt1: timer@e6130000 {
compatible = "renesas,r8a7795-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 302>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 302>;
status = "disabled";
};
cmt2: timer@e6140000 {
compatible = "renesas,r8a7795-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6140000 0 0x1004>;
interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 301>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 301>;
status = "disabled";
};
cmt3: timer@e6148000 {
compatible = "renesas,r8a7795-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6148000 0 0x1004>;
interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 300>;
clock-names = "fck";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 300>;
status = "disabled";
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a7795-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
......@@ -1836,7 +1906,7 @@
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
clocks = <&cpg CPG_MOD 1005>,
......
......@@ -68,6 +68,7 @@
ports {
/* rsnd_port0 is on salvator-common */
rsnd_port1: port@1 {
reg = <1>;
rsnd_endpoint1: endpoint {
remote-endpoint = <&dw_hdmi0_snd_in>;
......
......@@ -1775,7 +1775,7 @@
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
clocks = <&cpg CPG_MOD 1005>,
......@@ -2162,17 +2162,6 @@
dma-names = "rx", "tx";
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
};
};
};
audma0: dma-controller@ec700000 {
......
......@@ -317,6 +317,76 @@
reg = <0 0xe6060000 0 0x50c>;
};
cmt0: timer@e60f0000 {
compatible = "renesas,r8a77965-cmt0",
"renesas,rcar-gen3-cmt0";
reg = <0 0xe60f0000 0 0x1004>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 303>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 303>;
status = "disabled";
};
cmt1: timer@e6130000 {
compatible = "renesas,r8a77965-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 302>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 302>;
status = "disabled";
};
cmt2: timer@e6140000 {
compatible = "renesas,r8a77965-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6140000 0 0x1004>;
interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 301>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 301>;
status = "disabled";
};
cmt3: timer@e6148000 {
compatible = "renesas,r8a77965-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6148000 0 0x1004>;
interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 300>;
clock-names = "fck";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 300>;
status = "disabled";
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a77965-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
......@@ -1461,7 +1531,7 @@
<0 0xec5a0000 0 0x100>, /* ADG */
<0 0xec540000 0 0x1000>, /* SSIU */
<0 0xec541000 0 0x280>, /* SSI */
<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
<0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
clocks = <&cpg CPG_MOD 1005>,
......@@ -1585,56 +1655,267 @@
};
};
rcar_sound,ssiu {
ssiu00: ssiu-0 {
dmas = <&audma0 0x15>, <&audma1 0x16>;
dma-names = "rx", "tx";
};
ssiu01: ssiu-1 {
dmas = <&audma0 0x35>, <&audma1 0x36>;
dma-names = "rx", "tx";
};
ssiu02: ssiu-2 {
dmas = <&audma0 0x37>, <&audma1 0x38>;
dma-names = "rx", "tx";
};
ssiu03: ssiu-3 {
dmas = <&audma0 0x47>, <&audma1 0x48>;
dma-names = "rx", "tx";
};
ssiu04: ssiu-4 {
dmas = <&audma0 0x3F>, <&audma1 0x40>;
dma-names = "rx", "tx";
};
ssiu05: ssiu-5 {
dmas = <&audma0 0x43>, <&audma1 0x44>;
dma-names = "rx", "tx";
};
ssiu06: ssiu-6 {
dmas = <&audma0 0x4F>, <&audma1 0x50>;
dma-names = "rx", "tx";
};
ssiu07: ssiu-7 {
dmas = <&audma0 0x53>, <&audma1 0x54>;
dma-names = "rx", "tx";
};
ssiu10: ssiu-8 {
dmas = <&audma0 0x49>, <&audma1 0x4a>;
dma-names = "rx", "tx";
};
ssiu11: ssiu-9 {
dmas = <&audma0 0x4B>, <&audma1 0x4C>;
dma-names = "rx", "tx";
};
ssiu12: ssiu-10 {
dmas = <&audma0 0x57>, <&audma1 0x58>;
dma-names = "rx", "tx";
};
ssiu13: ssiu-11 {
dmas = <&audma0 0x59>, <&audma1 0x5A>;
dma-names = "rx", "tx";
};
ssiu14: ssiu-12 {
dmas = <&audma0 0x5F>, <&audma1 0x60>;
dma-names = "rx", "tx";
};
ssiu15: ssiu-13 {
dmas = <&audma0 0xC3>, <&audma1 0xC4>;
dma-names = "rx", "tx";
};
ssiu16: ssiu-14 {
dmas = <&audma0 0xC7>, <&audma1 0xC8>;
dma-names = "rx", "tx";
};
ssiu17: ssiu-15 {
dmas = <&audma0 0xCB>, <&audma1 0xCC>;
dma-names = "rx", "tx";
};
ssiu20: ssiu-16 {
dmas = <&audma0 0x63>, <&audma1 0x64>;
dma-names = "rx", "tx";
};
ssiu21: ssiu-17 {
dmas = <&audma0 0x67>, <&audma1 0x68>;
dma-names = "rx", "tx";
};
ssiu22: ssiu-18 {
dmas = <&audma0 0x6B>, <&audma1 0x6C>;
dma-names = "rx", "tx";
};
ssiu23: ssiu-19 {
dmas = <&audma0 0x6D>, <&audma1 0x6E>;
dma-names = "rx", "tx";
};
ssiu24: ssiu-20 {
dmas = <&audma0 0xCF>, <&audma1 0xCE>;
dma-names = "rx", "tx";
};
ssiu25: ssiu-21 {
dmas = <&audma0 0xEB>, <&audma1 0xEC>;
dma-names = "rx", "tx";
};
ssiu26: ssiu-22 {
dmas = <&audma0 0xED>, <&audma1 0xEE>;
dma-names = "rx", "tx";
};
ssiu27: ssiu-23 {
dmas = <&audma0 0xEF>, <&audma1 0xF0>;
dma-names = "rx", "tx";
};
ssiu30: ssiu-24 {
dmas = <&audma0 0x6f>, <&audma1 0x70>;
dma-names = "rx", "tx";
};
ssiu31: ssiu-25 {
dmas = <&audma0 0x21>, <&audma1 0x22>;
dma-names = "rx", "tx";
};
ssiu32: ssiu-26 {
dmas = <&audma0 0x23>, <&audma1 0x24>;
dma-names = "rx", "tx";
};
ssiu33: ssiu-27 {
dmas = <&audma0 0x25>, <&audma1 0x26>;
dma-names = "rx", "tx";
};
ssiu34: ssiu-28 {
dmas = <&audma0 0x27>, <&audma1 0x28>;
dma-names = "rx", "tx";
};
ssiu35: ssiu-29 {
dmas = <&audma0 0x29>, <&audma1 0x2A>;
dma-names = "rx", "tx";
};
ssiu36: ssiu-30 {
dmas = <&audma0 0x2B>, <&audma1 0x2C>;
dma-names = "rx", "tx";
};
ssiu37: ssiu-31 {
dmas = <&audma0 0x2D>, <&audma1 0x2E>;
dma-names = "rx", "tx";
};
ssiu40: ssiu-32 {
dmas = <&audma0 0x71>, <&audma1 0x72>;
dma-names = "rx", "tx";
};
ssiu41: ssiu-33 {
dmas = <&audma0 0x17>, <&audma1 0x18>;
dma-names = "rx", "tx";
};
ssiu42: ssiu-34 {
dmas = <&audma0 0x19>, <&audma1 0x1A>;
dma-names = "rx", "tx";
};
ssiu43: ssiu-35 {
dmas = <&audma0 0x1B>, <&audma1 0x1C>;
dma-names = "rx", "tx";
};
ssiu44: ssiu-36 {
dmas = <&audma0 0x1D>, <&audma1 0x1E>;
dma-names = "rx", "tx";
};
ssiu45: ssiu-37 {
dmas = <&audma0 0x1F>, <&audma1 0x20>;
dma-names = "rx", "tx";
};
ssiu46: ssiu-38 {
dmas = <&audma0 0x31>, <&audma1 0x32>;
dma-names = "rx", "tx";
};
ssiu47: ssiu-39 {
dmas = <&audma0 0x33>, <&audma1 0x34>;
dma-names = "rx", "tx";
};
ssiu50: ssiu-40 {
dmas = <&audma0 0x73>, <&audma1 0x74>;
dma-names = "rx", "tx";
};
ssiu60: ssiu-41 {
dmas = <&audma0 0x75>, <&audma1 0x76>;
dma-names = "rx", "tx";
};
ssiu70: ssiu-42 {
dmas = <&audma0 0x79>, <&audma1 0x7a>;
dma-names = "rx", "tx";
};
ssiu80: ssiu-43 {
dmas = <&audma0 0x7b>, <&audma1 0x7c>;
dma-names = "rx", "tx";
};
ssiu90: ssiu-44 {
dmas = <&audma0 0x7d>, <&audma1 0x7e>;
dma-names = "rx", "tx";
};
ssiu91: ssiu-45 {
dmas = <&audma0 0x7F>, <&audma1 0x80>;
dma-names = "rx", "tx";
};
ssiu92: ssiu-46 {
dmas = <&audma0 0x81>, <&audma1 0x82>;
dma-names = "rx", "tx";
};
ssiu93: ssiu-47 {
dmas = <&audma0 0x83>, <&audma1 0x84>;
dma-names = "rx", "tx";
};
ssiu94: ssiu-48 {
dmas = <&audma0 0xA3>, <&audma1 0xA4>;
dma-names = "rx", "tx";
};
ssiu95: ssiu-49 {
dmas = <&audma0 0xA5>, <&audma1 0xA6>;
dma-names = "rx", "tx";
};
ssiu96: ssiu-50 {
dmas = <&audma0 0xA7>, <&audma1 0xA8>;
dma-names = "rx", "tx";
};
ssiu97: ssiu-51 {
dmas = <&audma0 0xA9>, <&audma1 0xAA>;
dma-names = "rx", "tx";
};
};
rcar_sound,ssi {
ssi0: ssi-0 {
interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
dma-names = "rx", "tx", "rxu", "txu";
dmas = <&audma0 0x01>, <&audma1 0x02>;
dma-names = "rx", "tx";
};
ssi1: ssi-1 {
interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
dma-names = "rx", "tx", "rxu", "txu";
dmas = <&audma0 0x03>, <&audma1 0x04>;
dma-names = "rx", "tx";
};
ssi2: ssi-2 {
interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
dma-names = "rx", "tx", "rxu", "txu";
dmas = <&audma0 0x05>, <&audma1 0x06>;
dma-names = "rx", "tx";
};
ssi3: ssi-3 {
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
dma-names = "rx", "tx", "rxu", "txu";
dmas = <&audma0 0x07>, <&audma1 0x08>;
dma-names = "rx", "tx";
};
ssi4: ssi-4 {
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
dma-names = "rx", "tx", "rxu", "txu";
dmas = <&audma0 0x09>, <&audma1 0x0a>;
dma-names = "rx", "tx";
};
ssi5: ssi-5 {
interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
dma-names = "rx", "tx", "rxu", "txu";
dmas = <&audma0 0x0b>, <&audma1 0x0c>;
dma-names = "rx", "tx";
};
ssi6: ssi-6 {
interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
dma-names = "rx", "tx", "rxu", "txu";
dmas = <&audma0 0x0d>, <&audma1 0x0e>;
dma-names = "rx", "tx";
};
ssi7: ssi-7 {
interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
dma-names = "rx", "tx", "rxu", "txu";
dmas = <&audma0 0x0f>, <&audma1 0x10>;
dma-names = "rx", "tx";
};
ssi8: ssi-8 {
interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
dma-names = "rx", "tx", "rxu", "txu";
dmas = <&audma0 0x11>, <&audma1 0x12>;
dma-names = "rx", "tx";
};
ssi9: ssi-9 {
interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
dma-names = "rx", "tx", "rxu", "txu";
dmas = <&audma0 0x13>, <&audma1 0x14>;
dma-names = "rx", "tx";
};
};
};
......@@ -2166,7 +2447,6 @@
du: display@feb00000 {
compatible = "renesas,du-r8a77965";
reg = <0 0xfeb00000 0 0x80000>;
reg-names = "du";
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
......
/* SPDX-License-Identifier: GPL-2.0 */
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the ebisu board
*
......@@ -19,7 +19,7 @@
};
chosen {
bootargs = "ignore_loglevel";
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
......@@ -337,6 +337,15 @@
&i2c0 {
status = "okay";
io_expander: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gpio2>;
interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
};
hdmi-encoder@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
......@@ -398,7 +407,7 @@
};
port@a {
reg = <0xa>;
reg = <10>;
adv7482_txa: endpoint {
clock-lanes = <0>;
......@@ -440,6 +449,28 @@
};
};
&i2c_dvfs {
status = "okay";
clock-frequency = <400000>;
pmic: pmic@30 {
pinctrl-0 = <&irq0_pins>;
pinctrl-names = "default";
compatible = "rohm,bd9571mwv";
reg = <0x30>;
interrupt-parent = <&intc_ex>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
rohm,ddr-backup-power = <0x1>;
rohm,rstbmode-level;
};
};
&lvds0 {
status = "okay";
......@@ -458,6 +489,13 @@
};
&lvds1 {
/*
* Even though the LVDS1 output is not connected, the encoder must be
* enabled to supply a pixel clock to the DU for the DPAD output when
* LVDS0 is in use.
*/
status = "okay";
clocks = <&cpg CPG_MOD 727>,
<&x13_clk>,
<&extal_clk>;
......@@ -495,6 +533,11 @@
function = "du";
};
irq0_pins: irq0 {
groups = "intc_ex_irq0";
function = "intc_ex";
};
pwm3_pins: pwm3 {
groups = "pwm3_b";
function = "pwm3";
......@@ -650,6 +693,10 @@
status = "okay";
};
&vin5 {
status = "okay";
};
&xhci0 {
pinctrl-0 = <&usb30_pins>;
pinctrl-names = "default";
......
/* SPDX-License-Identifier: GPL-2.0 */
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the R-Car E3 (R8A77990) SoC
*
......@@ -284,6 +284,76 @@
status = "disabled";
};
cmt0: timer@e60f0000 {
compatible = "renesas,r8a77990-cmt0",
"renesas,rcar-gen3-cmt0";
reg = <0 0xe60f0000 0 0x1004>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 303>;
clock-names = "fck";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 303>;
status = "disabled";
};
cmt1: timer@e6130000 {
compatible = "renesas,r8a77990-cmt1",
"renesas,rcar-gen3-cmt1";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,