- Jul 27, 2021
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Function spl_boot_mode() is called in common/spl/spl_mmc.c, to find the boot mode for a given boot device. This function was renamed to spl_mmc_boot_mode() by commit e9759065. Therefore, rename spl_boot_mode to spl_mmc_boot_mode. Fixes: 57dba04a ("arm: mach-k3: am642: Add support for boot device detection") Signed-off-by:
Aswath Govindraju <a-govindraju@ti.com> Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726152807.22991-2-a-govindraju@ti.com -
CONFIG_SPL_TEXT_BASE was set to 0x70000000 in the commit, "26f32c32 configs: am64x_evm_*_defconfig: Rearrange the components in SRAM to satisfy the limitations for USB DFU boot mode". This change seems to have been dropped during a merge commit. Therefore, fix this by setting CONFIG_SPL_TEXT_BASE to 0x70000000. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210726145840.18977-1-a-govindraju@ti.com -
Add documentation for loading firmwares to be used by remote cores in the system including the environment variables that has to be set to load the firmwares. Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-21-kishon@ti.com -
Move j721e document from board/ti/j721e/README to doc/board/ti/j721e_evm.rst after converting it to RST format. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-20-kishon@ti.com -
Add CONFIG_PREBOOT to provide an automatic and easier way to configure ethernet PHY before loading the firmware. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-19-kishon@ti.com -
MAIN CPSW0 requires the PHY to be powered on and reset for QSGMII operation. Add a env variable to configure driving "0" on ENET_EXP_PWRDN controlled by GPIO EXPANDER2 (I2C Addr: 0x22), PIN: 17 and driving "1" on ENET_EXP_RESETZ controlled by GPIO EXPANDER2 (I2C Addr: 0x22), PIN: 18. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com> Link: https://lore.kernel.org/r/20210721155849.20994-18-kishon@ti.com
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Add config for torrent serdes and common clock framework. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-17-kishon@ti.com -
Enable the mmio mux driver, the J721E-wiz PHy driver and the cadence sierra phy driver. All of them are required for USB3 support Signed-off-by:
Jean-Jacques Hiblot <jjhiblot@ti.com> Signed-off-by:
Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-16-kishon@ti.com -
Add u-boot tags for torrent serdes. This has properties specific to u-boot on top of DT in v5.13 Linux Kernel. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-15-kishon@ti.com -
Add default lane function for torrent serdes. This is in sync with v5.13 Linux Kernel. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-14-kishon@ti.com -
Add DT node for torrent serdes. This is in sync with v5.13 Linux Kernel. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-13-kishon@ti.com -
Configure the parent clock of wiz3_pll0_refclk to the internal clock required for USB3 to be functional and also remove "ti,usb2-only" property as it now supports USB3 mode. This has properties specific to u-boot on top of DT present in v5.13 of Linux Kernel. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-12-kishon@ti.com -
Add support for probing and configuring Torrent serdes on J7200. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-11-kishon@ti.com -
Add support for WIZ module present in TI's J721E SoC. WIZ is a SERDES wrapper used to configure some of the input signals to the SERDES. It is used with both Sierra(16G) and Torrent(10G) SERDES. This driver configures three clock selects (pll0, pll1, dig) and supports resets for each of the lanes. This is an adaptation of the linux driver. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-10-kishon@ti.com -
Add driver for Torrent SERDES. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-9-kishon@ti.com -
Add a Sierra PHY driver with PCIe and USB support. This driver is a port from the mainline linux driver. The PHY has multiple lanes, which can be configured into groups, and a generic PHY device is created for each group. There are two resets controlling the overall PHY block, one to enable the APB interface for programming registers, and another to enable the PHY itself. Additionally there are resets for each PHY lane. The PHY can be configured in hardware to read register settings from ROM, or they can be written by the driver. The sequence of operation on startup is to enable the APB bus, write the PHY registers (if required) for each lane group, and then enable the PHY. Each group of lanes can then be individually controlled using the power_on()/ power_off() function for that generic PHY One difference with the linux driver is that the PHY is always reset after it is powered-on. This is because role switching is not supported in u-boot and the cable orientation is handled by the PHY reset. Signed-off-by:
Alan Douglas <adouglas@cadence.com> Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-8-kishon@ti.com -
AM64 has a single lane SERDES which can be configured to be used with either PCIe or USB. Define the possilbe values for the SERDES function in AM64 SoC here. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-7-kishon@ti.com -
Add defines for refclk driver used to route the refclk out of torrent SERDES. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-6-kishon@ti.com -
Add defines for AM64 SERDES Wrapper. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-5-kishon@ti.com -
Add definitions for additional phy types that's used specifically for Torrent SERDES. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210721155849.20994-4-kishon@ti.com -
Add test to check node name ignoring unit address. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org> Link: https://lore.kernel.org/r/20210721155849.20994-3-kishon@ti.com
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Add helper to compare node names. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: -
The SanCloud BeagleBone Enhanced (BBE) includes a Gigabit Ethernet PHY. Signed-off-by:Paul Barker <paul.barker@sancloud.com>
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This device tree is imported from Linux 5.13.1 and enabled via the am335x board file and the am335x evm defconfig. Signed-off-by: -
These device trees are updated to match the versions in Linux 5.13.1. The tick-timer entry in am335x-bone-common.dtsi is preserved. Signed-off-by: -
These headers are updated to match the versions in Linux 5.13.1. Signed-off-by: -
Enable configs to add support for HS400 speed mode. Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210525093826.10390-4-a-govindraju@ti.com -
HS400 speed mode is now supported in J7200 SoC[1]. Therefore add mmc-hs400-1_8v tag in sdhci0 device tree node. Also update the delay values for various speed modes supported, based on the revised january 2021 J7200 datasheet[2]. [1] - section 12.3.6.1.1 MMCSD Features, in https://www.ti.com/lit/ug/spruiu1a/spruiu1a.pdf, (SPRUIU1A – JULY 2020 – REVISED JANUARY 2021) [2] - https://www.ti.com/lit/ds/symlink/dra821u.pdf , (SPRSP57B – APRIL 2020 – REVISED JANUARY 2021) Signed-off-by:Lokesh Vutla <lokeshvutla@ti.com>
Link: https://lore.kernel.org/r/20210525093826.10390-3-a-govindraju@ti.com -
Read the strobe select value from the device tree property ti,strobe-sel, required for HS400 speed mode Fixes: a20008ea ("mmc: am654_sdhci: Add Support for configuring PHY in J721e") Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Link: https://lore.kernel.org/r/20210525093826.10390-2-a-govindraju@ti.com
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Enable HS400 speed mode by writing to HOST_CONTROL2 register. Signed-off-by:
Faiz Abbas <faiz_abbas@ti.com> Signed-off-by:
Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: -
Tom Rini authored
Signed-off-by:Tom Rini <trini@konsulko.com>
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- Jul 26, 2021
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https://source.denx.de/u-boot/custodians/u-boot-microblazeTom Rini authored
Xilinx changes for v2021.10-rc1 xilinx: - Use default ENVL_NOWHERE configuration - Add support for handling compressed kernels zynqmp: - SPL malloc size extension - USB2.0 for zc1751 dc2 - Fix USB3.0 nodes - Handle lpd_lsbus clock - Cleanup macros around SYSRESET versal: - Remove PBSIZE macro zynq_sdhci: - Tap delay fixups net: - Add support for MRMAC
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Manish Narani authored
Move the PHY properties from DWC3 node to USB node in ZynqMP DTs as here the USB3 PHY used is PSGTR, which is connected to Xilinx USB core. This PHY initialization should be handled from Xilinx USB core as the prerequisite register configurations are done here only. Signed-off-by:
Manish Narani <manish.narani@xilinx.com> Signed-off-by:
Michal Simek <michal.simek@xilinx.com>
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Raju Kumar Pothuraju authored
Add kernel_comp_addr_r, kernel_comp_size env variables for zynqmp and versal to be able to use the compressed kernel Image(.gz,.bz2,.lzma,.lzo) using booti command. Signed-off-by:
Raju Kumar Pothuraju <raju.kumar-pothuraju@xilinx.com> Signed-off-by:
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Michal Simek authored
It is default value which had been converted by commit 432e3980 ("include/configs: drop default definitions of CONFIG_SYS_PBSIZE"). That's why also remove it. Signed-off-by:
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Michal Simek authored
reset and poweroff are called via hooks in psci driver which is going around sysreset framework that's why enable sysreset drivers and do reset and poweroff via this framework. Using this flow will allow us to call SYSTEM_WARM_RESET based on psci 1.1 spec which can be calles with reset -w command. Signed-off-by: -
Michal Simek authored
The SPL can also be compiled with sysreset drivers just fine, so update the condition to cater for that option. The same change was done by commit efa1a62a ("ARM: imx8m: Do not define do_reset() if sysreset is enabled"). Signed-off-by:
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Michal Simek authored
CONFIG_SYSRESET_CMD_POWEROFF defines do_poweroff() in sysreset-uclass.c that's why don't define it twice when both CONFIG_SYSRESET_CMD_POWEROFF and CONFIG_CMD_POWEROFF are enabled. CONFIG_SYSRESET_CMD_POWEROFF depends on CONFIG_CMD_POWEROFF. Signed-off-by: -
Ashok Reddy Soma authored
Enable Xilinx AXI MRMAC for Versal platforms. Signed-off-by:
Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by:
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Ashok Reddy Soma authored
Add support for xilinx multirate(MRMAC) ethernet driver. This driver uses multichannel DMA(MCDMA) for data transfers of MRMAC. Added support for 4 ports of MRMAC for speeds 10G and 25G. MCDMA supports upto 16 channels but in this driver we have setup only one channel which is enough. Tested 10G and 25G on all 4 ports. Signed-off-by:
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