- Apr 29, 2021
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https://source.denx.de/u-boot/custodians/u-boot-cfi-flashTom Rini authored
- mtd: cfi: Fix PPB lock status readout (Marek)
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https://source.denx.de/u-boot/custodians/u-boot-marvellTom Rini authored
- Add base support for Marvell OcteonTX2 CN9130 CRB (mostly done by Kostya) - Sync Armada 3k/7k/8k SERDES code with Marvell version (misc Marvell authors) - pci-aardvark: Fix processing PIO transfers (Pali)
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Trying to clear PIO_START register when it is non-zero (which indicates that previous PIO transfer has not finished yet) causes an External Abort with SError 0xbf000002. This bug is currently worked around in TF-A by handling External Aborts in EL3 and ignoring this particular SError. This workaround was also discussed at: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50 https://lore.kernel.org/linux-pci/20190316161243.29517-1-repk@triplefau.lt/ https://lore.kernel.org/linux-pci/971be151d24312cc533989a64bd454b4@www.loen.fr/ https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1541 Implement a proper fix to prevent this External Abort. As it is not possible to cancel a pending PIO transfer, simply do not start a new one if previous has not finished yet. In this case return an error to the caller. In most cases this SError happens when there is no PCIe card connected or when PCIe link is down. The reason is that in these cases a PIO transfer takes about 1.44 seconds. For this reason we also increase the wait timeout in pcie_advk_wait_pio() to 1.5 seconds. If PIO read transfer for PCI_VENDOR_ID register times out, or if it isn't possible to read it yet because previous transfer is not finished, return Completion Retry Status value instead of failing, to give the caller a chance to send a new read request. Signed-off-by:
Pali Rohár <pali@kernel.org> Reviewed-by:
Marek Behún <marek.behun@nic.cz> Reviewed-by:
Stefan Roese <sr@denx.de>
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Change-Id: I29094afb646744afe78ad09bb7479894d1a65e96 Signed-off-by:Igal Liberman <igall@marvell.com>
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- Add additional step which enables the Impedance and PLL calibration. - Enable old squelch detector instead of the new analog squelch detector circuit and update host disconnect threshold value. - Update LS TX driver strength coarse and fine adjustment values. Change-Id: Ifa0a585bfb5ecab0bfa033eed6874ff98b16a7df Signed-off-by:Grzegorz Jaszczyk <jaz@semihalf.com>
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In CP115, comphy4 can be configured into SFI port1 (in addition to SFI0). This patch adds the option described above. In addition, rename all existing SFI/XFI references: COMPHY_TYPE_SFI --> COMPHY_TYPE_SFI0 No functional change for exsiting configuration. Change-Id: If9176222e0080424ba67347fe4d320215b1ba0c0 Signed-off-by:
Konstantin Porotchkin <kostap@marvell.com>
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According to Design Reference Specification the PHY PLL and Calibration register from PHY0 are shared for multi-port PHY. PLL control registers inside other PHY channels are not used. This commit reworks utmi device tree nodes in a way that common PHY PLL registers are moved to main utmi node. Accordingly both child nodes utmi-unit range is reduced and register offsets in utmi_phy.h are updated to this change. This fixes issues in scenarios when only utmi port1 was in use, which resulted with lack of correct pll initialization. Change-Id: Icc520dfa719f43a09493ab31f671efbe88872097 Signed-off-by: -
New products can contain up to 6 usb ports, therefore allow to initialize all relevant UTMI PHYs. Change-Id: I28c36e59fa0e3e338bb3ee0cee2240b923f39785 Signed-off-by:
Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
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It helps ATF to determine who called power off function (U-boot/Linux) and act accordingly Change-Id: Icfc5cbfdba64754496812154272b28c0ff639f0f Signed-off-by:
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- the default value of comphy pipe selector is set to PCIe (x4) in case of unconnected comphy the default value remains 0x4 which may lead to several issues with comphy initialization. - this patch adds SMC call that powers off the comphy lane in case of unconnected comphy. Change-Id: I196b2916518dd8df3b159ffa85e2989b8e483087 Signed-off-by:
Christine Gharzuzi <chrisg@marvell.com> Signed-off-by:
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Currently, we don't pass id for SGMII 0/1. A bug in comphy selector configuration was found (in comphy firmware), after fixing it, SGMII0/1 have different configuration, so we need to pass the ID the firmware. Change-Id: Idcff4029cc9cf018278e493221b64b33574e0d38 Signed-off-by:
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Change-Id: I358792a96c13b54e700c05227cc7a8f6bd584694 Signed-off-by:
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Now the comphy configuration is handled in atf, therefore there is no need to configure phy or pipe selector in u-boot, it is configured by atf for each particular pair: lane and mode. Change-Id: I0bebf8d5ff66dbeb6bf9ef90876195938a8eb705 Signed-off-by:
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Replace the XFI training with appropriate SMC call, so the firmware will perform exact initialization. Update Stefan 2021-03-23: Move comphy_smc() function to an earlier place - necessary for the mainline merge. Change-Id: I789b130b05529dc80dadcf66aef407d93595b762 Signed-off-by:
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Replace the comphy initialization for USB with appropriate SMC call, so the firmware will execute required serdes configuration. Change-Id: I7f773c0dfac70db9dd2653de2cdcfac577e78c4e Signed-off-by: -
Replace the comphy initialization for RXAUI with appropriate SMC call, so the firmware will execute required serdes configuration. Change-Id: Iedae0285fb283e05bb263a8b4ce46e8e7451a309 Signed-off-by:
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Even if comphy types of SATA2/SATA3/SGMII3 and comphy speeds of 1.5G/3G/6.25G were referenced in the driver non configuration (dts) was using it. This patch removes unused definitions. Change-Id: I53ed6f9d3a82b9d18cb4e488bc14d3cf687f9488 Signed-off-by:
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Change-Id: I3b97253e7102a0868440a9e0200acc1c7919c743 Signed-off-by: -
This patch adds support for running RX training using new command called "rx_training" Usage: rx_training - rx_training <cp id> <comphy id> RX training allows to improve link quality (for SFI mode) by running training sequence between us and the link partner, this allows to reach better link quality then using static configuration. Change-Id: I818fe67ccaf19a87af50d4c34a9db7d6802049a5 Signed-off-by:
Marcin Wojtas <mw@semihalf.com>
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This allows the lower level driver access to comphy map data (required for RX training support, which is introduced in the following patches). Change-Id: Ib7ffdc4b32076c01c3a5d33f59552c9dfc6b12fa Signed-off-by: -
If fdtdec_get_int can't find speed, set COMPHY_SPEED_INVALID If fdtdec_get_int can't find type, set COMPHY_TYPE_INVALID Move the error print if phy-type is invalid Add continue to the probe loop (in a case of invalid phy) Cosmetic changes Change-Id: I0c61b40bfe685437426fe907942ed338b7845378 Signed-off-by: -
Add UTMI analog parameters initialization values according to latest ETP. Change-Id: I5bcca205a3995202a18ff126f371a81f69e205c8 Signed-off-by: -
UTMI should be initialized only for enabled device tree nodes. This fix overrides current internal configuration array entry with the next DT entry data if error is detected during the current DT entry parsing or the current port is disabled. This way the internal configuration structure will only contain valid ports information obtained from the DT. Change-Id: I9c43c6a5d234e15ae9005d1c9bc983fc1f3544b8 Signed-off-by:
Omri Itach <omrii@marvell.com> Signed-off-by:
Ken Ma <make@marvell.com>
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In get_speed_string() we have an array (speed_strings[]) which includes all possible speed strings. This array size and content must be aligned to the speed defines in comphy_data.h. This patch adds missing 5.125G speed, aligns speed_strings[] and fixes incorrect printing when speed > 5.0G. Change-Id: I9900d23595094be321be0c62fcaa88036324568e Signed-off-by: -
Currently, all comphy definitions are PHY_TYPE_XX and PHY_SPEEED_XX. Those definition might be confused with MDIO PHY definitions. This patch does the following changes: - PHY_TYPE_XX --> COMPHY_TYPE_XX - PHY_SPEED_XX --> COMPHY_SPEED_XX This improves readability, no functional change. Change-Id: I2bd1d9289ebbc5c16fa80f9870f797ea1bcaf5fa Signed-off-by:
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- For some Marvell SoCs, like armada-3700, there are both USB host and device controller, but on PHY level the configuration is the same. - The new type supports both USB device and USB host - This patch is cherry-picked from u-boot-2015 as-is. Change-Id: I01262027edd8ec23391cff6fb409b3009aedfbb9 Signed-off-by:
jinghua <jinghua@marvell.com> Signed-off-by:
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Stefan Roese authored
Because of the incorrectly supported SGMII_2500 mode, this patch disables eth2 for now until this issue will be fixed in mainline. Also fix an incorrect comment. Signed-off-by: -
This patch adds the base support for the Marvell Octeon TX2 CN9130 CRB. Not all interfaces are supported fully yet. Signed-off-by:
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This patch adds the dtsi/dts files needed to support the Marvell Octeon TX2 CN9130 CRB. This is only the base port with not all interfaces supported fully. Signed-off-by:
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Move the default environment location to the end of 4MB flash region. This change allows to accomodate larger flash boot images making space for forthcoming code changes. Signed-off-by:
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Add support for SoCs based on AP807 die. Remove unused include file for Armada-8020 SoC. Signed-off-by:
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Use a single dtsi file for CP110 die instead of master/slave. Moving to single file will allow miltiple DTSI inclusions with re-defined CP index and name. This change will also allow support for SoCs containing more than two CP110 dies on board. Move pin control definitions from CP110 DTS to board DTS files Signed-off-by:
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- fix the dependency for MMC boot (add XENON to MVEBU_MMC) - fix the bubt destination assignment (missing # in "else" case) Signed-off-by:
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Add support for regulator-force-boot-off DT property. This property can be used by the board/device drivers for turning off regulators on early init stages as pre-requisite for the other components initialization. Signed-off-by:
Jaehoon Chung <jh80.chung@samsung.com>
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- Apr 28, 2021
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https://source.denx.de/u-boot/custodians/u-boot-amlogicTom Rini authored
- net: designware: fix PHY reset with DM_MDIO, fixing boot of (at least) Odroid-C4
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Neil Armstrong authored
The dw_eth_pdata is not accessible from the mdio device, it gets the mdio bus plat leading to random sleeps (-10174464 on Odroid-HC4). This moves the dw_mdio_reset function to a common one taking the ethernet device as parameter and use it from the dw_mdio_reset and dm_mdio variant functions. Fixes: 5160b456 ("net: designware: add DM_MDIO support") Reported-by:
Mark Kettenis <mark.kettenis@xs4all.nl> Signed-off-by:
Neil Armstrong <narmstrong@baylibre.com> Reviewed-by:
Ramon Fried <rfried.dev@gmail.com>
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Marek Vasut authored
For systems which use generic PHY support and implement USB PHY driver, the parsing of PHY properties is unnecessary, disable it. Signed-off-by:
Marek Vasut <marex@denx.de> Tested-by:
Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
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According to S26KL512S datasheet [1] and S29GL01GS datasheet [2], the procedure to read out PPB lock bits is to send the PPB Entry, PPB Read, Reset/ASO Exit. Currently, the code does send incorrect PPB Entry, PPB Read and Reset/ASO Exit is completely missing. The PPB Entry sent is implemented by sending flash_unlock_seq() and flash_write_cmd(..., FLASH_CMD_READ_ID). This translates to sequence 0x555:0xaa, 0x2aa:0x55, 0x555:0x90=FLASH_CMD_READ_ID. However, both [1] and [2] specify the last byte of PPB Entry as 0xc0=AMD_CMD_SET_PPB_ENTRY instead of 0x90=FLASH_CMD_READ_ID, that is 0x555:0xaa, 0x2aa:0x55, 0x555:0xc0=AMD_CMD_SET_PPB_ENTRY. Since this does make sense, this patch fixes it and thus also aligns the code in flash_get_size() with flash_real_protect(). The PPB Read returns 00h in case of Protected state and 01h in case of Unprotected state, according to [1] Note 83 and [2] Note 17, so invert the result. Moreover, align the arguments with similar code in flash_real_protect(). Finally, Reset/ASO Exit command should be executed to exit the PPB mode, so add the missing reset. [1] https://www.cypress.com/file/213346/download Document Number: 001-99198 Rev. *M Table 40. Command Definitions, Nonvolatile Sector Protection Command Set Definitions [2] https://www.cypress.com/file/177976/download Document Number: 001-98285 Rev. *R Table 7.1 Command Definitions, Nonvolatile Sector Protection Command Set Definitions Fixes: 03deff43 ("cfi_flash: Read PPB sector protection from device for AMD/Spansion chips") Signed-off-by:
Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Stefan Roese <sr@denx.de> Reviewed-by:
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Rsync all defconfig files using moveconfig.py Signed-off-by:Tom Rini <trini@konsulko.com>
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