1. 20 Feb, 2020 6 commits
  2. 02 Dec, 2019 1 commit
  3. 27 Nov, 2019 1 commit
  4. 06 Sep, 2019 1 commit
  5. 31 Jul, 2019 1 commit
  6. 17 Jul, 2019 4 commits
  7. 15 Jul, 2019 2 commits
  8. 03 May, 2019 2 commits
  9. 15 Jun, 2018 1 commit
  10. 31 May, 2018 1 commit
  11. 15 May, 2018 1 commit
  12. 11 May, 2018 5 commits
  13. 07 May, 2018 1 commit
    • Tom Rini's avatar
      SPDX: Convert all of our single license tags to Linux Kernel style · 83d290c5
      Tom Rini authored
      
      
      When U-Boot started using SPDX tags we were among the early adopters and
      there weren't a lot of other examples to borrow from.  So we picked the
      area of the file that usually had a full license text and replaced it
      with an appropriate SPDX-License-Identifier: entry.  Since then, the
      Linux Kernel has adopted SPDX tags and they place it as the very first
      line in a file (except where shebangs are used, then it's second line)
      and with slightly different comment styles than us.
      
      In part due to community overlap, in part due to better tag visibility
      and in part for other minor reasons, switch over to that style.
      
      This commit changes all instances where we have a single declared
      license in the tag as both the before and after are identical in tag
      contents.  There's also a few places where I found we did not have a tag
      and have introduced one.
      Signed-off-by: Tom Rini's avatarTom Rini <trini@konsulko.com>
      83d290c5
  14. 02 May, 2018 1 commit
    • Hannes Schmelzer's avatar
      mmc: sdhci: add SDHCI_QUIRK_BROKEN_HISPD_MODE · 88a57125
      Hannes Schmelzer authored and Jaehoon Chung's avatar Jaehoon Chung committed
      Some IP-core implementations of the SDHCI have different troubles on the
      silicon where they are placed.
      
      On ZYNQ platform for example Xilinx doesn't accept the hold timing of an
      eMMC chip which operates in High-Speed mode and must be forced to
      operate in non high-speed mode. To get rid of this
      "SDHCI_QUIRK_BROKEN_HISPD_MODE" is introduced.
      
      For more details about this refer to the Xilinx answer-recor #59999
      https://www.xilinx.com/support/answers/59999.html
      
      
      
      This commit:
      - doesn't set HISPD bit on the host-conroller
      - reflects this fact within the host-controller capabilities
      
      Upon this the layer above (mmc-driver) can setup the card correctly.
      
      Otherwise the MMC card will be switched into high-speed mode and causes
      possible timing violation on the host-controller side.
      Signed-off-by: default avatarHannes Schmelzer <oe5hpm@oevsv.at>
      Signed-off-by: default avatarHannes Schmelzer <hannes.schmelzer@br-automation.com>
      88a57125
  15. 22 Jan, 2018 2 commits
  16. 12 Jan, 2018 2 commits
  17. 17 Aug, 2017 1 commit
  18. 15 May, 2017 1 commit
    • Wenyou Yang's avatar
      mmc: sdhci: Fix maximum clock for programmable clock mode · 0e0dcc19
      Wenyou Yang authored and Jaehoon Chung's avatar Jaehoon Chung committed
      
      
      In the programmable clock mode, the SDCLK frequency is incorrectly
      assigned when the maximum clock has been assigned during probe,
      this causes the SDHCI not work well.
      
      In the programmable clock mode, when calculating the SDCLK Frequency
      Select, when the maximum clock has been assigned, it is the actual
      value, should not be multiplied by host->clk_mul. Otherwise, the
      maximum clock is multiplied host->clk_mul by the base clock achieved
      from the BASECLKF field of the Capabilities 0 Register.
      Signed-off-by: default avatarWenyou Yang <wenyou.yang@atmel.com>
      0e0dcc19
  19. 14 Apr, 2017 1 commit
    • Alex Deymo's avatar
      mmc: sdhci: Wait for SDHCI_INT_DATA_END when transferring. · 7dde50d7
      Alex Deymo authored and Jaehoon Chung's avatar Jaehoon Chung committed
      
      
      sdhci_transfer_data() function transfers the blocks passed up to the
      number of blocks defined in mmc_data, but returns immediately once all
      the blocks are transferred, even if the loop exit condition is not met
      (bit SDHCI_INT_DATA_END set in the STATUS word).
      
      When doing multiple writes to mmc, returning right after the last block
      is transferred can cause the write to fail when sending the
      MMC_CMD_STOP_TRANSMISSION command right after the
      MMC_CMD_WRITE_MULTIPLE_BLOCK command, leaving the mmc driver in an
      unconsistent state until reboot. This error was observed in the rpi3
      board.
      
      This patch waits for the SDHCI_INT_DATA_END bit to be set even after
      sending all the blocks.
      
      Test: Reliably wrote 2GiB of data to mmc in a rpi3.
      Signed-off-by: default avatarAlex Deymo <deymo@google.com>
      Reviewed-by: Simon Glass's avatarSimon Glass <sjg@chromium.org>
      7dde50d7
  20. 29 Mar, 2017 1 commit
  21. 21 Mar, 2017 1 commit
  22. 25 Jan, 2017 2 commits
    • Stefan Roese's avatar
      mmc: sdhci: Add support for optional controller specific set_ios_post() · 210841c6
      Stefan Roese authored
      
      
      Some SDHCI drivers might need to do some special controller configuration
      after the common clock set_ios() function has been called (speed / width
      configuration). This patch adds a call to the newly created function
      set_ios_port() when its configured in the host driver.
      
      This will be used by the Xenon SDHCI controller driver used on the
      Marvell Armada 3700 and 7k/8k ARM64 SoCs.
      Signed-off-by: Stefan Roese's avatarStefan Roese <sr@denx.de>
      Cc: Jaehoon Chung <jh80.chung@samsung.com>
      Cc: Simon Glass <sjg@chromium.org>
      Reviewed-by: Jaehoon Chung's avatarJaehoon Chung <jh80.chung@samsung.com>
      210841c6
    • Stefan Roese's avatar
      mmc: sdhci: Clear SDHCI_CLOCK_CONTROL before configuring the new value · 899fb9e3
      Stefan Roese authored
      
      
      This patch completely clears the SDHCI_CLOCK_CONTROL register before the
      new value is configured instead of just clearing the 2 bits
      SDHCI_CLOCK_CARD_EN and SDHCI_CLOCK_INT_EN. Without this change, some
      clock configurations will lead to the "Internal clock never stabilised."
      error message on the Xenon SDHCI controller used on the Marvell Armada
      3700 and 7k/8k ARM64 SoCs.
      
      The Linux SDHCI core driver also writes 0 to this register before
      the new value is configured. So this patch simplifies the driver a bit
      and brings the U-Boot driver more in-line with the Linux one.
      Signed-off-by: Stefan Roese's avatarStefan Roese <sr@denx.de>
      Cc: Jaehoon Chung <jh80.chung@samsung.com>
      Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
      Cc: Michal Simek <michal.simek@xilinx.com>
      Reviewed-by: Jaehoon Chung's avatarJaehoon Chung <jh80.chung@samsung.com>
      899fb9e3
  23. 23 Jan, 2017 1 commit